research-article

Macro-Aware Row-Style Power Delivery Network Design for Better Routability

Authors:

Jai-Ming Lin,

Jhih-Sheng Syu,

I-Ru ChenAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/3240765.3240824

Published: 05 November 2018 Publication History

Abstract

Reliability of a P/G network is one of the most important concerns in a chip design, which makes powerplanning the most critical step in the physical design. Traditional P/G network design mainly focuses on reducing usage of routing resource to satisfy voltage drop and electromigration constraints according to a regular mesh. As the number of macros in a modern design increases, this style may waste more routing resource and make routing congestion more severe in local regions. In order to save routing resource and increase routability, this paper proposes a delicate powerplanning method. First, we propose a row-style power mesh to facilitate connection of pre-placed macros and increase routability of signal nets in the later stage. Besides, an effective power stripe width which can reduce wastage of routing resource and provide stronger supply voltage is found. Moreover, we propose the first work to use the linear programming algorithm to minimize P/G routing area and consider routability at the same time. The experimental results show that routability of a design with many macros can be significantly improved by our row-style power networks.

References

[1]

S. Chowdhury, “Optimum design of reliable IC power networks having general graph topologies:” in Proceedings of DAC, pp. 787–790, 1989.

Google Scholar

[2]

C. Chu and Y.-C. Wong, “FLUTE: fast lookup table based rectilinear steiner minimal tree algorithm for VLSI design,” in IEEE TCAD, vol. 27, no. 1, pp. 70–83, Jan. 2008.

Google Scholar

[3]

W.-H. Chang, M.C.-T. Chao and S.-H. Chen, “Practical routability-driven design flow for multilayer power networks using aluminum-pad layer,” in IEEE TVLSI, vol. 22, no. 5, pp. 1069–1081, Jun. 2013.

Google Scholar

[4]

C.-C. Huang, C.-T. Lin, W.-S. Liao, C.-J. Lee, H.-M. Chen, C.-H. Lee and D.-M. Kwai, “Improving power delivery network design by practical methodologies,” in Proceedings of ICCD, pp. 237–242, 2014.

Google Scholar

[5]

Z. Li, Y. Ma, Q. Zhou, Y. Cai, Y. Wang, T. Huang, and Y. Xie, “Thermal-aware power network design for IR drop reduction in 3D ICs,” in Proceedings of ASP-DAC, pp. 47–52, 2012.

Google Scholar

[6]

S.S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin and C.-H. Lee, “Effective power network prototyping via statistical-based clustering and sequential linear programming,” in Proceedings of DATE, pp. 1701–1706, 2013.

Google Scholar

[7]

T. Mitsuhashi and E.S. Kuh, “Power and ground network topology optimization for cell based VLSIs,” in Proceedings of DAC, pp. 524–529, 1992.

Google Scholar

[8]

K. Shi, Z. Lin and Y.M. Jiang, “A power network synthesis method for industrial power gating designs,” in Proceedings of ISQED, pp. 362–367, 2007.

Google Scholar

[9]

X.-D. Tan, C.-J.R. Shi, D. Lungeanu, J.-C. Lee and L.-P. Yuan, “Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings,” in Proceedings of DAC, pp. 78–83, 2003.

Google Scholar

[10]

T.-Y. Wang and C.-C. Chen, “Optimization of the power/ground network wire-sizing and spacing based on sequential network simplex algorithm,” in Proceedings of ISQED, pp. 157–162, 2002.

Google Scholar

[11]

X.-H. Wu, C.-G. Qiao, L. Yin, and X.L. Hong, “Design and optimization of power/ground network for BBL-based VLSIs,” Acta Electronica Sinica, Aug. 2000.

Google Scholar

[12]

X. Wu, X. Hong, Y. Cai, Z. Luo, C.-K. Cheng, J. Gu, and W. Dai, “Area minimization of power distribution network using efficient nonlinear programming techniques,” in IEEE TCAD, vol. 23, no. 7, pp. 1086–1094, Jun. 2004.

Google Scholar

Cited By

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Lu CJiang IPeng CMohd Razha MUber AHui-Ru Jiang IPosser G(2024)Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability OptimizationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3633312(205-212)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3633312
Chen YChang HLiang YChang WTsai ILin CChang YChao M(2024)IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization2024 21st International SoC Design Conference (ISOCC)10.1109/ISOCC62682.2024.10762734(133-134)Online publication date: 19-Aug-2024
https://doi.org/10.1109/ISOCC62682.2024.10762734
Huang PChang Y(2023)Routability-driven Power/Ground Network Optimization Based on Machine LearningACM Transactions on Design Automation of Electronic Systems10.1145/358781728:4(1-27)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3587817
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Macro-Aware Row-Style Power Delivery Network Design for Better Routability
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)

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2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

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Published: 05 November 2018

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Lu CJiang IPeng CMohd Razha MUber AHui-Ru Jiang IPosser G(2024)Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability OptimizationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3633312(205-212)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3633312
Chen YChang HLiang YChang WTsai ILin CChang YChao M(2024)IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization2024 21st International SoC Design Conference (ISOCC)10.1109/ISOCC62682.2024.10762734(133-134)Online publication date: 19-Aug-2024
https://doi.org/10.1109/ISOCC62682.2024.10762734
Huang PChang Y(2023)Routability-driven Power/Ground Network Optimization Based on Machine LearningACM Transactions on Design Automation of Electronic Systems10.1145/358781728:4(1-27)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3587817
Hyun DLee WPark JShin Y(2023)Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard CellsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.323619070:6(2211-2215)Online publication date: Jun-2023
https://doi.org/10.1109/TCSII.2023.3236190
Lee WCho ICho GShin Y(2023)Routability-Driven Power Distribution Network Synthesis with IR-Drop Budgeting2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299845(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299845
Lin JKung YHuang ZChen ILienig JBehjat LYang S(2021)A Fast Power Network Optimization Algorithm for Improving Dynamic IR-dropProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447042(91-98)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3439706.3447042

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Routability-Driven Blockage-Aware Macro Placement

Design-hierarchy aware mixed-size placement for routability optimization

UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing

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