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PLATYPUS: a PLA test pattern generation tool

Authors:

Alberto Sangiovanni-VincentelliAuthors Info & Claims

DAC '85: Proceedings of the 22nd ACM/IEEE Design Automation Conference

Pages 197 - 203

Published: 01 June 1985 Publication History

Abstract

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced with other existing PLA tools such as the constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, “don't-care” bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.

References

[1]

H. Fleisher and L. I. Maissel, "An introduction to array logic," IBM I. Res. DeveZop., vol. 19,pp. 98-109,Mar. 1975.

Digital Library

[2]

R. Rudell, A. 5angiovanni-Vincentelli and G. De Mieh,li, "A Finite-S~a~~ Machine Synthesis System" Proc. 1985 Internat~mal Symposium on Circuits and Systems, Xyoto, Japan, 1985.

[3]

R. Proebsting, Electronics, p.82, Oct, 28,1976.

[4]

FXIill and G. Peterson, Introuctizm to swLtci~ing theory and h~gical design, Wiley,1981.

Digital Library

[5]

S. Bozorgui-Nesbat and E. J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," P~oc. 19&f International Test Conference, Philadelphia, October 1984.

[6]

K. Son and D. K. Pradhan, "Design of Programmable Logic Arrays for Testability," Proc. /EEE International Test Conference, November 11-13, 1980, pp163-166.

[7]

S. J. Hong and D. L. Ostapko, "FITPLA: A Programmable Logic Array for Function Independent Testing," Dig. lOth Int. S37np. FTC., Kyoto, Japan, 1980, pp131-136.

[8]

H. Fujiwara and K. Kinoshila, "A Design of Programmable logic Arrays with Universal Tests," IEEE Trans. o~ Comp., pp 823-828, Nov. 1981.

[9]

K.S. Ramana~ha and N. H. Biswas, "A Design for Teslability of Unde~ectable Crosspoint :Faults in Programmable Logic Arrays,* /EF, E Trans. on Colnp., June 1983.

[10]

K.A. Hun, J. Y. Jou and J. A. Abraham, "Built-In Tests For VLSI Finite- State Machines," Dig. o/ Papers 14th Irtt'l Con/. on Faul, t-Tolerant Computing, June 1984.

[11]

R. K. Brayton, G. D. Hachtel, C. T. McMullen and A. L. Sangiovanni- Vincentelli, "Logic Minimization Algorithms )'or VL$1 Synthesis," Kluwer Academic Publishers, 1984.

Digital Library

[12]

G. De Micheli and A. Sangiovanni-Vincen~:elli, "PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of programmable logic arrays," Proc. 20th Design Automation Conference. Miami Beach, FL., pp.530-537, June 1983.

Digital Library

[13]

G. De Micheli and M. Santomauro, " SMILE: A computer program for partitioning of programmed logic array,* Computer Aided Design. No. 2, pp. 89-97, March 1983 and Memorandum UCBIERL, No. 82/74.

[14]

G. Mah, "PANDA - a PLA generator for multiply folded arrays," M.S. Report, Dept. EECS, U.C. Berkeley 1983.

[15]

S. j. Hong and D. L. Ostapko, "Fault analy:ds and test generation for programmable logic arrays (PLA's),N ~ Trans. Comput., vol. C-28, pp.617 626, Sept. 1979.

[16]

C.W. Cha, " A testing strategy for PLAs," Proceedings o/the 15th Design Automation Con/erence, Las Vegas, NV, June 1978.

Digital Library

[17]

J. E, Smith, "Detection of faults in prog':ammable logic arrays," {EEE Trans. Comput., vol, C-28, pp. 845-853, Nov. 1979.

Digital Library

[18]

E.I. Muehldorf and T. W. Williams, "Optimized stuck fault test pattern generation for PLA macros," Digest o/Papers, 1977 Sernicondz~tor Test Sympos/z~n, pp.89-10I, Oct. 1977.

[19]

E.I. Muehldorf, G. P. Papp and T. W. Williams, *E{ficient test pattern generation for embedded PLAs," Proceedings of 1980 IEEE Test Conference. pp. 349-358, Sept. 1980.

[20]

E.B. Eichelberger and E. Lindbloom, "A heuristic test-pattern generator for programmable logic arrays,* IBMJ. Res. Develop, vol. 24, pp.15-22, Jan, 1980.

Digital Library

[21]

P. Bose and J. A. Abraham, "Test generation for programmable arrays," Proceedings of 19th Design Automation Conference, pp. 574-580, August 1982.

Digital Library

[22]

F. Somenzi, S, Gai, M. Mezzalama and P. Prinetto, "PART: programmable array testing based on a partitioning algorithm," IEEE Trans. CAD, vol. CAD-3, pp. 142-149, April 1984.

[23]

J. P. Roth, Computer Logic, Testing and 'teri~cation. Computer Scienc~ Press, 1980.

Digital Library

[24]

S.J. Hong, R. G. Gain and D. L. Os~apko, "MII~I: a heuristic approach for logic minimization," IBM)'. o/Res, and Dew., vol. 18,pp. 443-458, Sept. 1974.

Digital Library

[25]

Y. Tamir and C. H. Sequin, "Design and application of self-testing comparatots implemented with MOS PLA's," /EEE Trans. Comput., vol. C-33, pp. 493- 506.,June 1984.

[26]

M. Hofmann and A. R. Newton, "A Domino CMOS logic synthesis system," Proc. 1985 }nterTtational Symposium on Circuits amf Systems, June 1985.

[27]

R. Rudell, and A. Sangiovanni-Vincentelli, "I~PRESSO-MV: Algorithms for multiple-valued logic minimization," Proc. 198~: International Symposium on CircuLts and ~ystems, June 1985.

[28]

D. Landskov, S. Davidson, B.D. Shriver, and P.W. Mallett, "Local microcode compaction :~chntques," ACM Coraput.,.~-veys, vo}, i2, pp. 261-294, Sept. 1980.

Digital Library

Cited By

Farazmand NTahoori M(2009)Online detection of multiple faults in crossbar nano-architectures using dual rail implementationsProceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2009.5226346(79-82)Online publication date: 30-Jul-2009
https://dl.acm.org/doi/10.1109/NANOARCH.2009.5226346
Aas ENystu GAmbler TJess JDe Man H(1991)Experiments with autonomous test of PLAsProceedings of the conference on European design automation10.5555/951513.951623(503-509)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951623
Maxwell PWunderlich HAdshead GJess J(1990)The effectiveness of different test sets for PLAsProceedings of the conference on European design automation10.5555/949970.950112(628-632)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950112
Show More Cited By

Index Terms

PLATYPUS: a PLA test pattern generation tool
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '85: Proceedings of the 22nd ACM/IEEE Design Automation Conference

June 1985

838 pages

ISBN:0818606355

Chairmen:
Hillel Ofek
Silvar-Lisco, Menlo Park, CA
,
Lawrence A. O'Neill
AT&T Bell Labs, Holmdel, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

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IEEE Press

Publication History

Published: 01 June 1985

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Farazmand NTahoori M(2009)Online detection of multiple faults in crossbar nano-architectures using dual rail implementationsProceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2009.5226346(79-82)Online publication date: 30-Jul-2009
https://dl.acm.org/doi/10.1109/NANOARCH.2009.5226346
Aas ENystu GAmbler TJess JDe Man H(1991)Experiments with autonomous test of PLAsProceedings of the conference on European design automation10.5555/951513.951623(503-509)Online publication date: 25-Feb-1991
https://dl.acm.org/doi/10.5555/951513.951623
Maxwell PWunderlich HAdshead GJess J(1990)The effectiveness of different test sets for PLAsProceedings of the conference on European design automation10.5555/949970.950112(628-632)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950112
Zhu XBreuer M(1988)Analysis of Testable PLA DesignsIEEE Design & Test10.1109/54.79665:4(14-28)Online publication date: 1-Jul-1988
https://dl.acm.org/doi/10.1109/54.7966
Reddy SHa D(1987)A New Approach to the Design of Testable PLA'sIEEE Transactions on Computers10.1109/TC.1987.167688236:2(201-211)Online publication date: 1-Feb-1987
https://dl.acm.org/doi/10.1109/TC.1987.1676882
Ligthart MAarts EBeenker FThomas D(1986)Design-for-testability of PLA's using statistical coolingProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318066(339-345)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318066
Daehn WThomas D(1986)A unified treatment of PLA faults by Boolean differencesProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318065(334-338)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318065

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