[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/301177.301187acmconferencesArticle/Chapter ViewAbstractPublication PagesesweekConference Proceedingsconference-collections
Article
Free access

Instruction set selection for ASIP design

Published: 01 March 1999 Publication History
First page of PDF

References

[1]
ARC. Argonaut RISC cores, hup://www.risccoms.com.
[2]
ATHANS, P. M, AND SILVERMAN, H, F, Processor reconfignration through instruction,set metamorphosis. IEEE Computer 26, 3 (March 1993), I 1-18.
[3]
BUCHENRIEDER, K. HardwardSoflwareCo-Design: AnAnnotatedBibliogrophy. IT Press, Chicago, IL, 1994.
[4]
DE MICHELI,G, Computex-aldedhardware-anftwarecedesign. IEEE Micro 14, 4 (August ISK)4), 10-16.
[5]
ECKER. W. Using VHDL for HW/SW co-specification, In Proc, of the 1993 European Design and Automation Conference with EURO= VHDL "93 (Hmnburg, Germany, September 1993), R, Caraposano, F_A, GI, 1EEE Computer Society Press, pp. 500-505,
[6]
GSCHWlND, M. Hardware/Software Co-Evaluation of Instruction Sets, Phi) thesis, Technische Universitgt Wien, Vienna, Austria, July 1996,
[7]
GSCHWND. M., AN D MArinER, D. An extendible MIPS-I processor kecnel in VHDL for hardware/software co-designl In Prec. of the European Design Automation Conference EURO-DAC "96 with EURO-VHDL "96 (Geneva, Switzerland, Septembex 1996), GI, IEEE Computer Society Press, pp. 548-553.
[8]
GSCHWIND, M., AND PtETSCH, T, A smarl cache for improved vector perrefinance, In Proc, of the First International Meeting on Vector and Parallel Processing (Porto, Portugal, September 1993).
[9]
G. CHWIND, M., AND P{ETS CH, T, Vector prefetching, ACM Computer Architecture News 23, 5 (December 1995), 1-7.
[10]
GSCHWtND, M., SALAPURA, V., AND MAURER, D. FPGA prototyping of a RISC processor core for embedded applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1998). sobmittod.
[11]
GUPTA, R. K., COELHO, C. N., AND MICHELt, G. D, Synthesis and simulation of digital systems containing iumracfing hardware and software components. In Prec. of the 29th Design Automation Conference (DAC '92) (Anaheim, CA, June 1992).
[12]
HOLMER, B, K, A tool for processor instruction set design. In Prec. of the 1994 European Design Automation Conference with EURO-VHDL '94 (Grenoble, France, September 1994), IEEE Computer Society Press.
[13]
HUANG, I.- L, AND DISPAt N, A. M. Synthesis of instruction sets for pipelined microprocessors. In Prec. of the 31st Design Automation Conference fDAC '94) (San Diego, CA,tune 1994), ACId,
[14]
ISMAIL, T. B., ABID, M., O'BRIEN, K., AND JERRAYA, A. An approach for hardware-software codesign. In Proc, of Sth International Workshop on Rapid System Prowtyping (Grenoble, France, June 1994), IEEE, pp. 73-80.
[15]
KANE, G., AND HEtNR{CH, J. MIPS RlSCArchitecture: reference for the R2000, R3000, R6000 and the new R4000 instruction set computer architecture. Prentice-Hall, Englewood Cliffs, N J, 1992.
[16]
KRA LL, A An extended Prolog instruction set for RISC processors. In VLSI for Artificial Intelligence and Neural Networks (New York, NY, 1991), J. G. Delgndo-Frias and W. R. Moore, Eds., Plenum Press, pp. 101-108.
[17]
KRALL, A. The Vienna Abstrtat Machine. Journal of Logic Programming 29(1-3) (1996), 85--106.
[18]
KUULUSA, M., NURMI, J., TAKALA, J., OJALA, P., AND HERRANEN, H. A flexible DSP core for embedded systems. IEEE Design and Test of Computers 13, 4 (October 1997), 60--68.
[19]
MCMAHON, F. H. Lawrence Livermore National Laboratory FORTRAN Kernels Test: MFLOPS. FORTRAN source code, September 1991.
[20]
SALAPURA, V., AND GSCHWIND, M. Hawam/software co-design of a fuzzy RISe processor. In Prec. of the Design, Automation and Test in Europe Conference DATE "98 (Paris, France, February 1998), EDAA, IEEE Computer Society Press, pp. 875-882,
[21]
SAt'O, L, ALOMARY, A. Y., HONMA, Y., NAKATA, T., HIOMI, A., HIK1CH1, N, AND IMA1, M. PEAS-I: A hardware/software codesign system for ASIP development. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science E77-A, 3 (March 1994), 483-491.
[22]
SUCHER, R. Carmel: A configurable long instruction word DSP core. lu Micro. processor Forum 1998 (San lose, CA, Octobes 1998), MicroDesign Resources.
[23]
TORLEY, J. ARC getting full-30 licensces aboard. Microprocessor Report 12, 15 (November 1998).
[24]
TORLEY, J. LXR-4080 is independent implemenlation of basic MIPS-I processor core. Microprocessor Report I2, 2 (February 1998), 134
[25]
VAN PRAET, L, GOOSSENS, G, LANNEER, D, AND DE MAN, H. InStl'UC.tion set definition and insWuction set selection for ASIPs. In Proc. of the 7th International Symposium on High-Level Synthesis 1994 (Niagara on the Lake, ON, Canada, 1994), IEEE, pp. 11-16.
[26]
WOLF, W. H. Hardware-softwareeo-design ofembeddedsystems. Proceedings of the IEEE 82, 7 (July 1994), 967-989.

Cited By

View all
  • (2024)The Development of an Application-Specific Instruction Set Processor Specialized on a Convolutional Neural Network Trained on MNISTAdvances in Computational Collective Intelligence10.1007/978-3-031-70248-8_8(94-105)Online publication date: 8-Sep-2024
  • (2016)Architectural Support for Long Integer Modulo Arithmetic on Risc-Based Smart CardsThe International Journal of High Performance Computing Applications10.1177/109434200301700200417:2(135-146)Online publication date: 26-Jul-2016
  • (2013)A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set ProcessorsProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.154(7-12)Online publication date: 5-Jan-2013
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
CODES '99: Proceedings of the seventh international workshop on Hardware/software codesign
March 1999
216 pages
ISBN:1581131321
DOI:10.1145/301177
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 1999

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Conference

CODES99
Sponsor:

Acceptance Rates

CODES '99 Paper Acceptance Rate 40 of 98 submissions, 41%;
Overall Acceptance Rate 280 of 864 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)74
  • Downloads (Last 6 weeks)13
Reflects downloads up to 11 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2024)The Development of an Application-Specific Instruction Set Processor Specialized on a Convolutional Neural Network Trained on MNISTAdvances in Computational Collective Intelligence10.1007/978-3-031-70248-8_8(94-105)Online publication date: 8-Sep-2024
  • (2016)Architectural Support for Long Integer Modulo Arithmetic on Risc-Based Smart CardsThe International Journal of High Performance Computing Applications10.1177/109434200301700200417:2(135-146)Online publication date: 26-Jul-2016
  • (2013)A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set ProcessorsProceedings of the 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems10.1109/VLSID.2013.154(7-12)Online publication date: 5-Jan-2013
  • (2012)FISHIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.209054320:1(52-65)Online publication date: 1-Jan-2012
  • (2012)Instruction-set selection for multi-application based ASIP design: An instruction-level study2012 IEEE 6th International Conference on Information and Automation for Sustainability10.1109/ICIAFS.2012.6419895(141-146)Online publication date: Sep-2012
  • (2010)Enhancing the performance of symmetric-key cryptography via instruction set extensionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202517118:11(1505-1518)Online publication date: 1-Nov-2010
  • (2009)Optimal subgraph covering for customisable VLIW processorsIET Computers & Digital Techniques10.1049/iet-cdt:200701043:1(14)Online publication date: 2009
  • (2008)Accelerated AES implementations via generalized instruction set extensionsJournal of Computer Security10.5555/1370694.137069516:3(265-288)Online publication date: 1-Aug-2008
  • (2008)A Research on an ASIP Processing Element Architecture Suitable for FPGA ImplementationProceedings of the 2008 International Conference on Computer Science and Software Engineering - Volume 0310.1109/CSSE.2008.580(441-445)Online publication date: 12-Dec-2008
  • (2008)Instruction Set Extensions for Enhancing the Performance of Symmetric-Key CryptographyProceedings of the 2008 Annual Computer Security Applications Conference10.1109/ACSAC.2008.10(465-474)Online publication date: 8-Dec-2008
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media