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10.1145/3078468.3078487acmconferencesArticle/Chapter ViewAbstractPublication PagessystorConference Proceedingsconference-collections
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Putting the OS in control of DRAM with mapping aliases

Published: 22 May 2017 Publication History

Abstract

On multicore CPUs, processes compete for shared resources such as caches and memory. Sharing DRAM resources such as channels and banks can increase request latencies and thereby slow down applications [3]. In our experiments, we observe that slowdowns depend on the combination of workloads and can vary widely for a given benchmark.

References

[1]
L. Liu et al. BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating dram bank-/channel-level interferences in multicore systems. ACM Trans. Archit. Code Optim., Feb. 2014.
[2]
S. P. Muralidhara et al. Reducing memory interference in multicore systems via application-aware memory channel partitioning. In IEEE/ACM MICRO-44, pages 374--385, New York, NY, USA, 2011. ACM.
[3]
O. Mutlu et al. Research problems and opportunities in memory systems. Supercomputing Frontiers and Innovations: an Intern. Journal, 1(3):19--55, Oct. 2014.

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cover image ACM Conferences
SYSTOR '17: Proceedings of the 10th ACM International Systems and Storage Conference
May 2017
195 pages
ISBN:9781450350358
DOI:10.1145/3078468
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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  • TCE: Technion Computer Engineering Center
  • USENIX Assoc: USENIX Assoc

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 May 2017

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  1. DRAM partitioning
  2. dynamic DRAM address mapping

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