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Age-aware Logic and Memory Co-Placement for RRAM-FPGAs

Authors:

Jingtong HuAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 1, Pages 1 - 6

https://doi.org/10.1145/3061639.3062198

Published: 18 June 2017 Publication History

Abstract

Resistive RAM (RRAM) is a promising non-volatile memory (NVM) device which can replace traditional SRAM as on-chip storage for logic and data in FPGAs. While RRAM outperforms SRAM by offering high scalability, low leakage power, and near-zero power-on delay, RRAM-FPGAs have limited programming cycles, and different writes frequencies of memory and logic blocks make the challenge more severe. To overcome this endurance challenge, we propose an age-aware placement framework for RRAM-FPGAs with uniform reconfigurable logic/memory units. The framework, consisting of a dynamic reconfiguration region allocation algorithm and a logic/memory co-placement algorithm, balances write distributions across the entire FPGA according to logic and memory write frequency differences. The proposed algorithms have been integrated into the VTR synthesis flow. Experiments show that the framework achieves 94.9% write reduction, thus effectively extending RRAM-FPGA programming cycles.

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Cited By

Zhao MXu FZheng HZhang HXiong YJia ZCai X(2023)Correlation-guided Placement for Nonvolatile FPGAs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247963(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247963
Zheng HZhang HXu SXu FZhao M(2022)Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319768541:11(3591-3601)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2022.3197685
Zhang HZheng HLi SZhang YZhao MCai X(2022)Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAsJournal of Systems Architecture10.1016/j.sysarc.2022.102532128(102532)Online publication date: Jul-2022
https://doi.org/10.1016/j.sysarc.2022.102532
Show More Cited By

Age-aware Logic and Memory Co-Placement for RRAM-FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design

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Published In

cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

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National Science Foundation

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DAC '17

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SIGDA

DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Cited By

Zhao MXu FZheng HZhang HXiong YJia ZCai X(2023)Correlation-guided Placement for Nonvolatile FPGAs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247963(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247963
Zheng HZhang HXu SXu FZhao M(2022)Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319768541:11(3591-3601)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2022.3197685
Zhang HZheng HLi SZhang YZhao MCai X(2022)Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAsJournal of Systems Architecture10.1016/j.sysarc.2022.102532128(102532)Online publication date: Jul-2022
https://doi.org/10.1016/j.sysarc.2022.102532
Park SKim JYoon S(2020)Energy-aware Placement for SRAM-NVM Hybrid FPGAs2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116487(858-863)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116487
Lima JMoura RCarro L(2020)Leveraging reuse and endurance by efficient mapping and placement for NVM-based FPGAs2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS50870.2020.9159743(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/IOLTS50870.2020.9159743
Cardoso de Lima JBrandalero MCarro L(2020)Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM Arrays2020 30th International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL50879.2020.00018(40-46)Online publication date: Aug-2020
https://doi.org/10.1109/FPL50879.2020.00018
Huai SSong WZhao MCai XJia Z(2019)Performance-aware Wear Leveling for Block RAM in Nonvolatile FPGAsProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317881(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317881
Zhang JKwon MKim HKim HJung M(2019)FlashGPUProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317827(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317827
Yang CXue YHomayoun HTaskin BMohsenin TZhao W(2019)A Scalable and Process Variation Aware NVM-FPGA Placement AlgorithmProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317971(165-170)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317971
Zambelli CCastellari MOlivo PBertozzi D(2018)Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs2018 New Generation of CAS (NGCAS)10.1109/NGCAS.2018.8572050(21-24)Online publication date: Nov-2018
https://doi.org/10.1109/NGCAS.2018.8572050
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