extended-abstract

DRAMScale: Mechanisms to Increase DRAM Capacity

Authors:

Krishna T. Malladi,

Uksong Kang,

Manu Awasthi,

Hongzhong ZhengAuthors Info & Claims

MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

Pages 325 - 326

https://doi.org/10.1145/2989081.2989109

Published: 03 October 2016 Publication History

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Abstract

New resistive memory technologies promise scalability and non-volatility but suffer from longer, asymmetric read-write latencies and lower endurance, placing the burden of system design on architects. In order to avoid such pitfalls and still provision for exascale data requirements using a much faster DRAM technology, we introduce DRAMScale. It features three novel mechanisms to increase DRAM density while complementing technology scaling and creating a new capacity-optimized DRAM system. Such optimizations enable us to build a two-tier memory system that meets memory latency and capacity requirements.

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Cited By

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Singh GNadig RPark JBera RHajinazar NNovo DGómez-Luna JStuijk SCorporaal HMutlu OSalapura VZahran MChong FTang L(2022)SibylProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527442(320-336)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527442
Mohamed KMohamed K(2020)Near-Memory/In-Memory Computing: Pillars and LaddersNeuromorphic Computing and Beyond10.1007/978-3-030-37224-8_6(167-186)Online publication date: 26-Jan-2020
https://doi.org/10.1007/978-3-030-37224-8_6
Li YGhose SChoi JSun JWang HMutlu O(2017)Utility-Based Hybrid Memory Management2017 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER.2017.130(152-165)Online publication date: Sep-2017
https://doi.org/10.1109/CLUSTER.2017.130

DRAMScale: Mechanisms to Increase DRAM Capacity
1. Hardware
  1. Integrated circuits

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Published In

MEMSYS '16: Proceedings of the Second International Symposium on Memory Systems

October 2016

463 pages

ISBN:9781450343053

DOI:10.1145/2989081

General Chair:
Bruce Jacob
University of Maryland

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 October 2016

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MEMSYS '16

MEMSYS '16: The Second International Symposium on Memory Systems

October 3 - 6, 2016

VA, Alexandria, USA

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Cited By

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Singh GNadig RPark JBera RHajinazar NNovo DGómez-Luna JStuijk SCorporaal HMutlu OSalapura VZahran MChong FTang L(2022)SibylProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527442(320-336)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527442
Mohamed KMohamed K(2020)Near-Memory/In-Memory Computing: Pillars and LaddersNeuromorphic Computing and Beyond10.1007/978-3-030-37224-8_6(167-186)Online publication date: 26-Jan-2020
https://doi.org/10.1007/978-3-030-37224-8_6
Li YGhose SChoi JSun JWang HMutlu O(2017)Utility-Based Hybrid Memory Management2017 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER.2017.130(152-165)Online publication date: Sep-2017
https://doi.org/10.1109/CLUSTER.2017.130

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Challenges of High-Capacity DRAM Stacks and Potential Directions

Reduced latency DRAM for multi-core safety-critical real-time systems

Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?