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research-article

Virtual prototyping of floating point units

Authors:

Guillaume Sarrazin,

Nicolas Brunie,

Frédéric PétrotAuthors Info & Claims

RAPIDO '16: Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Article No.: 1, Pages 1 - 6

https://doi.org/10.1145/2852339.2852340

Published: 18 January 2016 Publication History

Abstract

Virtual prototyping is a key technology for design space exploration, design verification, code development and testing of new systems on chip. For processors, either general purpose, multi and manycore or GPUs, the availability of powerful floating point units has now become mandatory in a lot of markets. However, implementing a fast and accurate floating point unit virtual prototype is not easy, even if host and target processors are IEEE 754 compliant. The goal of this paper is not to propose a definitive solution to this problem, but to draw the attention of the virtual prototyping community to it. To that aim, we study two solutions that form a compromise between speed of virtual prototype execution and computation accuracy.

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Cited By

Zurstraßen NBosbach NJoseph JJünger LWeinstock JLeupers R(2023)Efficient RISC-V-on-x64 Floating Point Simulation2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00090(558-565)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00090
Badaroux MPétrot F(2021)Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary TranslationProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431416(325-330)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431416

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cover image ACM Other conferences

RAPIDO '16: Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

January 2016

41 pages

ISBN:9781450340724

DOI:10.1145/2852339

Copyright © 2016 ACM.

© 2016 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 January 2016

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RAPIDO '16

RAPIDO '16: Rapid Simulation and Performance Evaluation: Methods and Tools

January 18, 2016

Prague, Czech Republic

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Cited By

Zurstraßen NBosbach NJoseph JJünger LWeinstock JLeupers R(2023)Efficient RISC-V-on-x64 Floating Point Simulation2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00090(558-565)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00090
Badaroux MPétrot F(2021)Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary TranslationProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431416(325-330)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431416

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