Article

Free access

Speculative execution model with duplication

Authors:

Kei Hiraki,

Junji Tamatsukuri,

Takashi MatsumotoAuthors Info & Claims

ICS '98: Proceedings of the 12th international conference on Supercomputing

Pages 321 - 328

https://doi.org/10.1145/277830.277907

Published: 13 July 1998 Publication History

PDF eReader

References

[1]

T. Matsumoto, T. Tanaka, T. Moriyama, and S. Uzuhara: MiSC: A Mechanism for integrated Synchronization and Communication Using Snoop Caches. Proc. of the 1991 Int. Conf. on Parallel Processing, Vol. 1, pp. 161-170, 1991.

Google Scholar

[2]

Junji Tamatsukuri, Takashi Matsumoto, Kei Hiraki., "On-Chip Parallel Architecture for Runtime Loop Restructuring",Technical Report TR- 04,University of Tokyo, 1997

Google Scholar

[3]

Kazuki Yoshizoe, "Java Virtual Machine which speculatively executes loops in parallel", Bachelor Thesis, Department of information science, University of Tokyo, 1997.

Google Scholar

[4]

S. Lee and R. Gupta: Executing Loops on a Fine- Grained MiMD Architecture. Proc. of International Conference MICRO91, pp. 199-205, 1991.

Digital Library

Google Scholar

[5]

G. Sohi and S. Breach and T. Vijaykumar: Multiscalar Processors. Proc. of the 22nd Annual International Symposium on Computer Architecture, 1995.

Digital Library

Google Scholar

[6]

D. Burger, S. Kaxiras and J. R. Goodman: Datascalar Architectures, Proc. of the 24th Annual International Symposium on Computer Architecture, 1997.

Digital Library

Google Scholar

[7]

M. Franklin, G. Sohi: ARB:A Hardware Mechanism for Dynamic Reordering of Memory References. Technical report on University of Wisconsin-Madison, 1995

Google Scholar

[8]

D. Tullsen, S. Eggers, H. Levy: Simultaneous Multithreading:Maximizing On-Chip Parallelism. Proc. of the 22nd Annual International Symposium on Computer Architecture, 1995.

Digital Library

Google Scholar

[9]

D. Tullsen, S. Eggers, H. Levy: Exploiting Choice:Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. Proc. of the 23rd Annual International Symposium on Computer Architecture, 1996.

Digital Library

Google Scholar

[10]

K. Olukotun, B. Nayfeh, L. Hammond, K. Wilson and K. Chang: The Case for a Single-Chip Multiprocessor. Proc. of the 7th International Coniference of Architectural Support for Programming Languages and Operationg Systems, pp. 2-11, 1996.

Digital Library

Google Scholar

[11]

J. Oplinger, D. Heine, S .W .Liao, B. A. Nayfeh, M. S. Lam and K. Olukotun: Software and Hardware for Exploiting Speculative Parallelism with Multiprocessor, Technical report, Stanford University, 1997.

Digital Library

Google Scholar

[12]

J. Tsai, P. Yew: The Superthreaded Architecture:Thread Pipelining with Run-time Data Dependence Checking and Control Speculation. Proc. of The 4th International Conference on Parallel Architecture, 1996.

Digital Library

Google Scholar

[13]

R. M. Tomasulo: An efficient algorithm for exploring multiple arithmetic units, IBM Journal of Research and Development, Vol. 11, No. 1, pp. 25-33, 1967.

Digital Library

Google Scholar

[14]

M. D. Smith, M. Johnson, M. A. Horowitz: Limits on Multiple Instruction Issue. Proc. of the 3rd International Conference on Architectural Support for Programing Languages and Operating Systems, pp. 290-302, 1989.

Digital Library

Google Scholar

[15]

D. J. Kuck, R. H. Kuhn, D. A. Pauda, B. Leasure, M. Wolfe: Dependence Graphs And Compiler Optimizations. Proc. of the 8th Annual ACM Symposium on Principles of Programming Languages, pp. 207-218, 1981.

Digital Library

Google Scholar

[16]

R. Eickemeyer, S. Vassiliadis: A load-instruction unit for pipelined processors. IBM Journal of Research and Development, Vol. 37, No. 4, pp. 547- 524, 1993.

Digital Library

Google Scholar

[17]

M. S. Lam, R. P. Wilson: Limits of Control Flow on Parallelism. Proc. of the 19th Annual International Symposium on Computer Architecture, 1992.

Digital Library

Google Scholar

[18]

S. Damianakis, K. Li, A. Rogers: An Analysis of a Combined Hardware-software Mechanism for Speculative Loads. Technical Report No. 455 on Princeton University, 1994

Google Scholar

[19]

J. K. F. Lee, A. J. Smith : Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer, Vol. 17 (January 1984), pp. 6- 22.

Digital Library

Google Scholar

[20]

M. K. Lipasti, C.B. Wilkerson, J. P. Shen : Value Locality and Load Value Prediction. Proc. of the 7th International Conference on Architecutual Support for Plogramming Language and Operating Systems, 1996, pp. 138- 147

Digital Library

Google Scholar

[21]

P. K. Dubey, K. O'Brien, K. M. O'Brien, C. Barton: Single-Program Speculative Multithreading(SPSM) Architecture: Compilerassisted Fine-Grained Multithreading. Proc. Parallel Architectures and Compilation Techniques, IFIP 1995, pp. 109-121

Digital Library

Google Scholar

[22]

K. Ebcioglu, E. R. Altman: DAISY:Dynamic Compilation for 100% Architectural Compatibility, IBM Reserch Report RC 20538, 1996.

Google Scholar

Cited By

View all

Yang XZheng QChen GYao Z(2006)Reverse Compilation for Speculative Parallel ThreadingProceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies10.1109/PDCAT.2006.94(138-143)Online publication date: 4-Dec-2006
https://dl.acm.org/doi/10.1109/PDCAT.2006.94
Gontmakher AMendelson ASchuster AShklover G(2006)Speculative Synchronization and Thread Management for Fine Granularity ThreadsThe Twelfth International Symposium on High-Performance Computer Architecture, 2006.10.1109/HPCA.2006.1598136(283-292)Online publication date: 2006
https://doi.org/10.1109/HPCA.2006.1598136
Jordan AForenc JTudruj M(2005)Speculative parallel processing applied to modelling of initial problemsCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/0332164051057109324:1(127-144)Online publication date: 1-Mar-2005
https://doi.org/10.1108/03321640510571093
Show More Cited By

Recommendations

An evaluation of speculative instruction execution on simultaneous multithreaded processors

Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...
The impact of speculative execution on SMT processors

By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are ...
Support for speculative execution in high-performance processors

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICS '98: Proceedings of the 12th international conference on Supercomputing

July 1998

464 pages

ISBN:089791998X

DOI:10.1145/277830

Chairmen:
Greg Egan
Monash Univ.
,
Richard Brent
Oxford Univ.; and Australian National Univ., Canberra, Australia
,
Dennis Gannon
Indiana Univ.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 July 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICS98

Sponsor:

SIGARCH
IEEE-CS

ICS98: 1998 International Conference on Supercomputing

Melbourne, Australia

Acceptance Rates

Overall Acceptance Rate 629 of 2,180 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
384
Total Downloads

Downloads (Last 12 months)28
Downloads (Last 6 weeks)1

Reflects downloads up to 11 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Yang XZheng QChen GYao Z(2006)Reverse Compilation for Speculative Parallel ThreadingProceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies10.1109/PDCAT.2006.94(138-143)Online publication date: 4-Dec-2006
https://dl.acm.org/doi/10.1109/PDCAT.2006.94
Gontmakher AMendelson ASchuster AShklover G(2006)Speculative Synchronization and Thread Management for Fine Granularity ThreadsThe Twelfth International Symposium on High-Performance Computer Architecture, 2006.10.1109/HPCA.2006.1598136(283-292)Online publication date: 2006
https://doi.org/10.1109/HPCA.2006.1598136
Jordan AForenc JTudruj M(2005)Speculative parallel processing applied to modelling of initial problemsCOMPEL - The international journal for computation and mathematics in electrical and electronic engineering10.1108/0332164051057109324:1(127-144)Online publication date: 1-Mar-2005
https://doi.org/10.1108/03321640510571093
Ootsu KYokota TOno TBaba T(2002)Preliminary evaluation of a binary translation system for multithreaded processorsInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems10.1109/IWIA.2002.1035021(77-84)Online publication date: 2002
https://doi.org/10.1109/IWIA.2002.1035021
Forenc JJordan ATudruj M(2000)Speculative parallel processing applied to modelling of initial problems in electrical circuitsProceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 200010.1109/PCEE.2000.873627(192-196)Online publication date: 2000
https://doi.org/10.1109/PCEE.2000.873627

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

An evaluation of speculative instruction execution on simultaneous multithreaded processors

The impact of speculative execution on SMT processors

Support for speculative execution in high-performance processors