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Measuring flexibility in single-ISA heterogeneous processors

Authors:

Erik Tomusk,

Christophe Dubach,

Michael O'BoyleAuthors Info & Claims

PACT '14: Proceedings of the 23rd international conference on Parallel architectures and compilation

Pages 495 - 496

https://doi.org/10.1145/2628071.2628125

Published: 24 August 2014 Publication History

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Abstract

Single-ISA heterogeneous processors are a promising method for enabling runtime power flexibility. Low-priority programs run on low-power cores, and high-priority programs run on high-power cores. In recent years, a number of methods for heterogeneous design space exploration have emerged. These methods search the design space for Pareto frontiers of cores that are optimal for power and speed. We demonstrate that a heterogeneous processor cannot be composed by simply selecting some cores from a Pareto-optimal set; the selection must give even coverage of the design space. We then define a metric - clumpiness - for measuring how well selected heterogeneous cores cover the design space.

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Cited By

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Saeedi SBodin BWagstaff HNisbet ANardi LMawer JMelot NPalomar OVespa ESpink TGorgovan CWebb AClarkson JTomusk EDebrunner TKaszyk KGonzalez-De-Aledo PRodchenko ARiley GKotselidis CFranke BO Boyle MDavison AKelly PLujan MFurber S(2018)Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented RealityProceedings of the IEEE10.1109/JPROC.2018.2856739106:11(2020-2039)Online publication date: Nov-2018
https://doi.org/10.1109/JPROC.2018.2856739
Tomusk EDubach CO’boyle M(2015)Four Metrics to Evaluate Heterogeneous MulticoresACM Transactions on Architecture and Code Optimization10.1145/282995012:4(1-25)Online publication date: 16-Nov-2015
https://dl.acm.org/doi/10.1145/2829950

Index Terms

Measuring flexibility in single-ISA heterogeneous processors
1. General and reference
  1. Cross-computing tools and techniques
    1. Design
    2. Performance

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Information & Contributors

Information

Published In

PACT '14: Proceedings of the 23rd international conference on Parallel architectures and compilation

August 2014

514 pages

ISBN:9781450328098

DOI:10.1145/2628071

General Chair:
J. Nelson Amaral
University of Alberta, Canada
,
Program Chair:
Josep Torrellas
University of Illinois, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 August 2014

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PACT '14

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IFIP WG 10.3
SIGARCH
IEEE CS TCPP
IEEE CS TCAA

PACT '14: International Conference on Parallel Architectures and Compilation

August 24 - 27, 2014

AB, Edmonton, Canada

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PACT '14 Paper Acceptance Rate 54 of 144 submissions, 38%;

Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

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Saeedi SBodin BWagstaff HNisbet ANardi LMawer JMelot NPalomar OVespa ESpink TGorgovan CWebb AClarkson JTomusk EDebrunner TKaszyk KGonzalez-De-Aledo PRodchenko ARiley GKotselidis CFranke BO Boyle MDavison AKelly PLujan MFurber S(2018)Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented RealityProceedings of the IEEE10.1109/JPROC.2018.2856739106:11(2020-2039)Online publication date: Nov-2018
https://doi.org/10.1109/JPROC.2018.2856739
Tomusk EDubach CO’boyle M(2015)Four Metrics to Evaluate Heterogeneous MulticoresACM Transactions on Architecture and Code Optimization10.1145/282995012:4(1-25)Online publication date: 16-Nov-2015
https://dl.acm.org/doi/10.1145/2829950

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Index Terms

Recommendations

Selecting Heterogeneous Cores for Diversity

Workload and power budget partitioning for single-chip heterogeneous processors

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance