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VTR 7.0: Next Generation Architecture and CAD System for FPGAs

Authors:

Jeffrey Goeders,

Michael Wainberg,

Andrew Somerville,

Konstantin Nasartschuk,

Nooruddin Ahmed,

Kenneth B. Kent,

Jason Anderson,

Vaughn BetzAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Issue 2

Article No.: 6, Pages 1 - 30

https://doi.org/10.1145/2617593

Published: 04 July 2014 Publication History

Abstract

Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article describes recent advances in the open source Verilog-to-Routing (VTR) CAD flow that enable further research in these areas. VTR now supports designs with multiple clocks in both timing analysis and optimization. Hard adder/carry logic can be included in an architecture in various ways and significantly improves the performance of arithmetic circuits. The flow now models energy consumption, an increasingly important concern. The speed and quality of the packing algorithms have been significantly improved. VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. We also release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments. Finally, we show that while this version of VTR supports new and complex features, it has a 1.5× compile time speed-up for simple architectures and a 6× speed-up for complex architectures compared to the previous release, with no degradation to timing or wire-length quality.

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Cited By

Liu FPei ZYu ZZheng HHe ZChen TYu B(2024)CBTune: Contextual Bandit Tuning for Logic Synthesis2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546766(1-6)Online publication date: 25-Mar-2024
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Zhang HZhao MZheng HXiong YZhang YShen Z(2024)Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546738(1-6)Online publication date: 25-Mar-2024
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Gunter AWilton SAmrouch HHu JGarg SLin Y(2024)Machine Learning VLSI CAD Experiments Should Consider Atomic Data GroupsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685970(1-8)Online publication date: 9-Sep-2024
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Index Terms

VTR 7.0: Next Generation Architecture and CAD System for FPGAs
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Physical design (EDA)
      1. Placement
      2. Wire routing

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Information

Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 7, Issue 2

June 2014

199 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2638850

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 July 2014

Accepted: 01 March 2014

Revised: 01 February 2014

Received: 01 December 2013

Published in TRETS Volume 7, Issue 2

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Semiconductor Research Corporation
NSERC, SRC, Altera, and Texas Instruments
Natural Sciences and Engineering Research Council of Canada
Texas Instruments Inc.

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Cited By

Liu FPei ZYu ZZheng HHe ZChen TYu B(2024)CBTune: Contextual Bandit Tuning for Logic Synthesis2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546766(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546766
Zhang HZhao MZheng HXiong YZhang YShen Z(2024)Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546738(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546738
Gunter AWilton SAmrouch HHu JGarg SLin Y(2024)Machine Learning VLSI CAD Experiments Should Consider Atomic Data GroupsProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685970(1-8)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685970
Gunter AThomas MGhanathe NWilton SAmrouch HHu JGarg SLin Y(2024)Enabling Risk Management of Machine Learning Predictions for FPGA RoutabilityProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685969(1-9)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685969
Hassani FSadrosadati MRohbani NPointner SWille RSarbazi-azad H(2024)An Efficient FPGA Architecture with Turn-Restricted Switch BoxesACM Transactions on Design Automation of Electronic Systems10.1145/3643809Online publication date: 3-Feb-2024
https://doi.org/10.1145/3643809
Li YLi XShen HFan JXu YHuang K(2024)An All-digital Compute-in-memory FPGA Architecture for Deep Learning AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/364046917:1(1-27)Online publication date: 12-Feb-2024
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Rostami Sani SYe A(2024)Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nmACM Transactions on Reconfigurable Technology and Systems10.1145/363905517:1(1-29)Online publication date: 12-Feb-2024
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Abbaszadeh MHow DZhang ZPutnam A(2024)From Topology to Realization in FPGA/VPR RoutingProceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3626202.3637572(85-96)Online publication date: 1-Apr-2024
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Sudhanya PJoy Vasantha Rani S(2024)Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUTJournal of Circuits, Systems and Computers10.1142/S0218126625500598Online publication date: 30-Sep-2024
https://doi.org/10.1142/S0218126625500598
Li Y(2024)CFPara: a combination of coarse and fine-grained FPGA parallel routing methodsInternational Conference on Image, Signal Processing, and Pattern Recognition (ISPP 2024)10.1117/12.3033797(183)Online publication date: 13-Jun-2024
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