[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
research-article
Open access

Revisiting memory management on virtualized environments

Published: 01 December 2013 Publication History

Abstract

With the evolvement of hardware, 64-bit Central Processing Units (CPUs) and 64-bit Operating Systems (OSs) have dominated the market. This article investigates the performance of virtual memory management of Virtual Machines (VMs) with a large virtual address space in 64-bit OSs, which imposes different pressure on memory virtualization than 32-bit systems. Each of the two conventional memory virtualization approaches, Shadowing Paging (SP) and Hardware-Assisted Paging (HAP), causes different overhead for different applications. Our experiments show that 64-bit applications prefer to run in a VM using SP, while 32-bit applications do not have a uniform preference between SP and HAP. In this article, we trace this inconsistency between 32-bit applications and 64-bit applications to its root cause through a systematic empirical study in Linux systems and discover that the major overhead of SP results from memory management in the 32-bit GNU C library (glibc). We propose enhancements to the existing memory management algorithms, which substantially reduce the overhead of SP. Based on the evaluations using SPEC CPU2006, Parsec 2.1, and cloud benchmarks, our results show that SP, with the improved memory allocators, can compete with HAP in almost all cases, in both 64-bit and 32-bit systems. We conclude that without a significant breakthrough in HAP, researchers should pay more attention to SP, which is more flexible and cost effective.

References

[1]
Adams, K. and Agesen, O. 2006. A comparison of software and hardware techniques for x86 virtualization. ACM SIGOPS Operating Systems Review 40, 5, 2--13.
[2]
Ahn, J., Jin, S., and Huh, J. 2012. Revisiting hardware-assisted page walks for virtualized systems. In Proceedings of the 2012 39th Annual International Symposium on Computer Architecture (ISCA’12). IEEE, 476--487.
[3]
Barr, T. W., Cox, A. L., and Rixner, S. 2010. Translation caching: skip, don't walk (the page table). ACM SIGARCH Computer Architecture News 38, 3, 48--59.
[4]
Barr, T. W., Cox, A. L., and Rixner, S. 2011. SpecTLB: A mechanism for speculative address translation. In Proceedings of the 2011 38th Annual International Symposium on Computer Architecture (ISCA’11). IEEE, 307--317.
[5]
Berger, E. D., Zorn, B. G., and McKinley, K. S. 2002. Reconsidering custom memory allocation. ACM SIGPLAN Notices 37, 11, 1--12.
[6]
Berger, E. D., McKinley, K. S., Blumofe, R. D., and Wilson, P. R. 2000. Hoard: A scalable memory allocator for multithreaded applications. ACM SIGPLAN Notices 35, 11, 117--128.
[7]
Bhargava, R., Serebrin, B., Spadini, F., and Manne, S. 2008. Accelerating two-dimensional page walks for virtualized systems. ACM SIGARCH Computer Architecture News 36, 1, 26--35.
[8]
Bienia, C. and Li, K. 2009. Parsec 2.0: A new benchmark suite for chip-multiprocessors. In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation.
[9]
Chen, Y., Fang, S., Eeckhout, L., Temam, O., and Wu, C. 2012. Iterative optimization for the data center. ACM SIGARCH Computer Architecture News 40, 1, 49--60.
[10]
Ezolt, P. 2001. A study in Malloc: a case of excessive minor faults. In Proceedings of the 5th Annual Linux Showcase and Conference.
[11]
Ferreira, T. B., Matias, R., Macedo, A., and Araujo, L. B. 2011. An experimental study on memory allocators in multicore and multithreaded applications. In Proceedings of the 12th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT’11). IEEE, 92--98.
[12]
Gillespie, M. 2009. Best Practices for Paravirtualization Enhancements from Intel® virtualization technology: EPT and VT-d. Retrieved November 26, 2013 from http://software.intel.com/en-us/articles/best-practices-for-paravirtualization-enhancements-from-intel-virtualization-technology-ept-and-vt-d.
[13]
Gillick, D., Faria, A., and DeNero, J. 2006. MapReduce: Distributed computing for machine learning. Retrieved November 26, 2013 from http://www.icsi.berkeley.edu/∼arlo/publications/gillick_cs262a_proj.pdf.
[14]
Gloger, W. Wolfram Gloger's Malloc Homepage. Retrieved November 26, 2013 from http://www.malloc.de/en/.
[15]
Gu, Y. and Grossman, R. L. 2009. Sector and Sphere: The design and implementation of a high-performance data cloud. Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, 1897, 2429--2445.
[16]
Henning, J. L. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34, 4, 1--17.
[17]
Lea, D. A Memory Allocator. Retrieved November 26, 2013 from http://g.oswego.edu/dl/html/malloc.html.
[18]
Liu, Z., Li, H., and Miao, G. 2010. MapReduce-based backpropagation neural network over large scale mobile data. In Proceedings of the 2010 6th International Conference on Natural Computation (ICNC’10). IEEE, 1726--1730.
[19]
Menon, A., Cox, A. L., and Zwaenepoel, W. 2006. Optimizing network virtualization in Xen. In Proceedings of the USENIX Annual Technical Conference. 15--28.
[20]
Mytkowicz, T., Diwan, A., Hauswirth, M., and Sweeney, P. F. 2009. Producing wrong data without doing anything obviously wrong! ACM SIGPLAN Notices 44, 3, 265--276.
[21]
Santos, J. R., Turner, Y., Janakiraman, G., and Pratt, I. 2008. Bridging the gap between software and hardware techniques for i/o virtualization. In Proceedings of the USENIX’08 Annual Technical Conference.
[22]
Talluri, M. and Hill, M. D. 1994. Surpassing the TLB performance of superpages with less operating system support. 29, 11, 171--182.
[23]
Talluri, M., Kong, S., Hill, M. D., and Patterson, D. A. 1992. Tradeoffs in supporting two page sizes. In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA’92). 415--424.
[24]
Wang, X., Zang, J., Wang, Z., Luo, Y., and Li, X. 2011. Selective hardware/software memory virtualization. ACM SIGPLAN Notices 46, 7, 217--226.
[25]
Zhao, W., Wang, Z., and Luo, Y. 2009. Dynamic memory balancing for virtual machines. ACM SIGOPS Operating Systems Review 43, 3, 37--47.

Cited By

View all
  • (2016)Early execution time-estimation through automatically generated timing modelsReal-Time Systems10.1007/s11241-016-9250-752:6(731-760)Online publication date: 1-Nov-2016
  • (2015)A Light-Weighted Software-Controlled Cache for PCM-based Main Memory SystemsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840823(22-29)Online publication date: 2-Nov-2015
  • (2014)Integrating profile-driven parallelism detection and machine-learning-based mappingACM Transactions on Architecture and Code Optimization10.1145/257956111:1(1-26)Online publication date: 1-Feb-2014
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 10, Issue 4
December 2013
1046 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/2541228
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 2013
Accepted: 01 November 2013
Revised: 01 November 2013
Received: 01 June 2013
Published in TACO Volume 10, Issue 4

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Virtualization
  2. hardware-assisted paging
  3. memory allocation
  4. shadowing paging

Qualifiers

  • Research-article
  • Research
  • Refereed

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)262
  • Downloads (Last 6 weeks)68
Reflects downloads up to 11 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2016)Early execution time-estimation through automatically generated timing modelsReal-Time Systems10.1007/s11241-016-9250-752:6(731-760)Online publication date: 1-Nov-2016
  • (2015)A Light-Weighted Software-Controlled Cache for PCM-based Main Memory SystemsProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840823(22-29)Online publication date: 2-Nov-2015
  • (2014)Integrating profile-driven parallelism detection and machine-learning-based mappingACM Transactions on Architecture and Code Optimization10.1145/257956111:1(1-26)Online publication date: 1-Feb-2014
  • (2014)Accelerating the next generation long read mapping with the FPGA-based systemIEEE/ACM Transactions on Computational Biology and Bioinformatics10.1109/TCBB.2014.232687611:5(840-852)Online publication date: 1-Sep-2014

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Full Access

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media