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High-level symbolic construction technique for high performance sequential synthesis

Authors:

Andrew Seawright,

Forrest BrewerAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 424 - 428

https://doi.org/10.1145/157485.164961

Published: 01 July 1993 Publication History

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References

[1]

A. V. Aho, R. Sethi, and J. D. Ullman, Compilers Principles, Techniques, and Tools. Reading: Addison-Wesley 1988.]]

Digital Library

Google Scholar

[2]

K.S. Brace, R. L. Rudell, and R. E. Bryant, "Efficient Implemenation of a BDD Package," 27th DAC, pp. 40-45, June 1990.]]

Digital Library

Google Scholar

[3]

R. E. Bryant, "Graph Based Algorithms for Boolean Function Manipulation," IEEE T-CAD, pp. 677-691, Aug. 1986.]]

Digital Library

Google Scholar

[4]

S. Carlson, introduction to HDL-Based Design Using VHDL. Mountain View: Synopsys, 1990.]]

Google Scholar

[5]

O. Coudert, J. C. Madre, "A Unified Framework for the Formal Verification of Sequential Circuits," ICCAD-90, pp. 126-129, Nov. 1990.]]

Google Scholar

[6]

R.W. Floyd, and J. D. Ullman, "The Compilation of Regular Expressions into Integrated Circuits," Jo. ACM. 29:2, 1982.]]

Digital Library

Google Scholar

[7]

J. E. Hopcroft, J. D. Ullman, Introduction to Automata Theory, Languages, and Computation. Reading: Addison Wesley, 1986.]]

Digital Library

Google Scholar

[8]

M.A. Jackson, "Constructive Methods of Program Design,"Lecture Notes in Computer Science, Vol. 44, Springer-Verlag, pp. 236- 262, 1976.]]

Digital Library

Google Scholar

[9]

S.C. Johnson, "Yaee: Yet Another Compiler Compiler," Computhag Science Tech. Rep. 32, AT&T Bell Labs, Murray Hill, NJ 1975.]]

Google Scholar

[10]

A. R. Karlin, H. W. Trickey, and J. D. UUman, "Experience with a Regular Expression Compiler," ICCD, pp. 656-665, 1983.]]

Google Scholar

[11]

Z. Kohavi, Switching and Finite Automata. New York: McGraw- Hill, 1978.]]

Google Scholar

[12]

M. E. Lesk, "Lex -A Lexical Analyzer Generator," Computing Science Tech. Rep. 39, AT&T Bell Labs, Murray HilL NJ 1975.]]

Google Scholar

[13]

B. Lin, Synthesis of VZSl Designs with Symbolic Techniques, Ph. D. Thesis, Univ. of Calif., Berkeley, UCB/ERL M91/105, Nov. 1991.]]

Digital Library

Google Scholar

[14]

S. Malik, A. R. Wang, R. K. Brayton, A. Sangiovanni-V'mcentelli, "Logic Verification Using BDDs in a Logic Synthesis Environment," ICCAD-88, pp. 6-9 Nov. 1988.]]

Google Scholar

[15]

A. Seawright, F. Brewer, "Synthesis from Production-Based Specifications," 29th DAC, pp. 194-199, June 1992.]]

Digital Library

Google Scholar

[16]

H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. Sangiovanni-VincentellL "Implicit State Enumeration of Finite State Machines using BDD's," ICCAD-90 pp. 130-133, Nov. 1990.]]

Google Scholar

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Eisner CFisman D(2008)Augmenting a regular expression-based temporal logic with local variablesProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517447(1-8)Online publication date: 17-Nov-2008
https://dl.acm.org/doi/10.5555/1517424.1517447
Eisner CFisman D(2008)Augmenting a Regular Expression-Based Temporal Logic with Local Variables2008 Formal Methods in Computer-Aided Design10.1109/FMCAD.2008.ECP.27(1-8)Online publication date: Nov-2008
https://doi.org/10.1109/FMCAD.2008.ECP.27
Pasricha SDutt N(2008)Verification and Security Issues in On-Chip Communication Architecture DesignOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00010-4(367-402)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00010-4
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High-level symbolic construction technique for high performance sequential synthesis

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Eisner CFisman D(2008)Augmenting a regular expression-based temporal logic with local variablesProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517447(1-8)Online publication date: 17-Nov-2008
https://dl.acm.org/doi/10.5555/1517424.1517447
Eisner CFisman D(2008)Augmenting a Regular Expression-Based Temporal Logic with Local Variables2008 Formal Methods in Computer-Aided Design10.1109/FMCAD.2008.ECP.27(1-8)Online publication date: Nov-2008
https://doi.org/10.1109/FMCAD.2008.ECP.27
Pasricha SDutt N(2008)Verification and Security Issues in On-Chip Communication Architecture DesignOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00010-4(367-402)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00010-4
Boule MZilic Z(2007)Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware EmulationProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358006(324-329)Online publication date: 23-Jan-2007
https://dl.acm.org/doi/10.1109/ASPDAC.2007.358006
Hu ACasas JYang J(2003)Efficient Generation of Monitor Circuits for GSTE Assertion GraphsProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009884Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009884
Hu ACases JJin Yang (2003)Efficient generation of monitor circuits for GSTE assertion graphsICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159685(154-159)Online publication date: 2003
https://doi.org/10.1109/ICCAD.2003.159685
Hu ACasas JYang J(2003)Reasoning about GSTE Assertion GraphsCorrect Hardware Design and Verification Methods10.1007/978-3-540-39724-3_17(170-184)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39724-3_17
Oliveira MHu AAckland B(2002)High-Level specification and automatic generation of IP interface monitorsProceedings of the 39th annual Design Automation Conference10.1145/513918.513952(129-134)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513952
Oliveira MHu A(2002)High-level specification and automatic generation of IP interface monitorsProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)10.1109/DAC.2002.1012607(129-134)Online publication date: 2002
https://doi.org/10.1109/DAC.2002.1012607
Seawright ABrewer F(2001)ClairvoyantReadings in hardware/software co-design10.5555/567003.567036(375-388)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/567003.567036
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