research-article

A new paradigm for synthesis and propagation of clock gating conditions

Authors:

Ranan Fraer,

Gila Kamhi,

Muhammad K. MhameedAuthors Info & Claims

DAC '08: Proceedings of the 45th annual Design Automation Conference

Pages 658 - 663

https://doi.org/10.1145/1391469.1391638

Published: 08 June 2008 Publication History

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Abstract

Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are poorly gated or not gated at all. A second contribution of our paper is a robust and scalable approach to extract stability conditions for clock gating. Finally, we present a uniform treatment of unobservability and stability as dual approaches for propagating gating conditions forward and backward. Experimental results demonstrate significant power reduction (in the range of 14% -- 55% of the clock power) on Intel micro-processor designs.

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Bruttomesso R(2021)Intrepid: A Scriptable and Cloud-Ready SMT-Based Model CheckerFormal Methods for Industrial Critical Systems10.1007/978-3-030-85248-1_13(202-211)Online publication date: 19-Aug-2021
https://doi.org/10.1007/978-3-030-85248-1_13
Udupi SUrdahl JStoffel DKunz W(2019)Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design FlowsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.2906820(1-14)Online publication date: 2019
https://doi.org/10.1109/TVLSI.2019.2906820
Yang GKim T(2018)Design and Algorithm for Clock Gating and Flip-flop Co-optimization2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3240793(1-6)Online publication date: 5-Nov-2018
https://dl.acm.org/doi/10.1145/3240765.3240793
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Index Terms

A new paradigm for synthesis and propagation of clock gating conditions
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

DAC '08: Proceedings of the 45th annual Design Automation Conference

June 2008

993 pages

ISBN:9781605581156

DOI:10.1145/1391469

General Chair:
Limor Fix
Intel Research Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 June 2008

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DAC '08

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SIGDA

DAC '08: The 45th Annual Design Automation Conference 2008

June 8 - 13, 2008

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Bruttomesso R(2021)Intrepid: A Scriptable and Cloud-Ready SMT-Based Model CheckerFormal Methods for Industrial Critical Systems10.1007/978-3-030-85248-1_13(202-211)Online publication date: 19-Aug-2021
https://doi.org/10.1007/978-3-030-85248-1_13
Udupi SUrdahl JStoffel DKunz W(2019)Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design FlowsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.2906820(1-14)Online publication date: 2019
https://doi.org/10.1109/TVLSI.2019.2906820
Yang GKim T(2018)Design and Algorithm for Clock Gating and Flip-flop Co-optimization2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1145/3240765.3240793(1-6)Online publication date: 5-Nov-2018
https://dl.acm.org/doi/10.1145/3240765.3240793
Udupi SUrdahl JStoffel DKunz W(2017)Dynamic Power Optimization Based on Formal Property Checking of Operations2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.56(227-232)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.56
Nawrot RKulisz JKania D(2017)Synthesis of energy-efficient FSMs implemented in PLD circuits10.1063/1.5012395(120003)Online publication date: 2017
https://doi.org/10.1063/1.5012395
Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Lam TTang WWei XDiao YYu‐LiangWu D(2016)ApplicationsBoolean Circuit Rewiring10.1002/9781118750124.ch5(133-210)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch5
Zhang ZChen DDai SCampbell K(2015)High-level Synthesis for Low-power DesignIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.128(12-25)Online publication date: 2015
https://doi.org/10.2197/ipsjtsldm.8.12
Yi JKim J(2015)Power modeling for digital circuits with clock gatingIEICE Electronics Express10.1587/elex.12.2015081712:24(20150817-20150817)Online publication date: 2015
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Riahi Alam MSalehi Nasab MFakhraie S(2015)Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock GatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244573434:12(1954-1963)Online publication date: Dec-2015
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