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Issues and challenges in compiling for the CBEA

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LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

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https://doi.org/10.1145/1254766.1254786

Published: 13 June 2007 Publication History

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Abstract

It has been demonstrated that expert programmers can develop and hand tune applications to exploit the full performance potential of the CBE architecture. We believe that sophisticated compiler optimization technology can bridge the gap between usability and performance in this arena. To this end we have developed a research prototype compiler targeting the Cell processor.

In this talk we describe a variety of compiler techniques to exploit the Cell processor. These techniques are aimed at automatically generating high quality codes for the heterogeneous parallelism available on the Cell processor. In particular we will focus the discussion on managing the small local memories of the SPEs and discuss our approach to presenting the user with a single shared memory image through our compiler controlled software cache. We will also report and discuss the results we have achieved to date, which indicate that significant speedup can be achieved on this processor with a high level of support from the compiler.

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Yan MZhao PYang ZLi S(2009)Exploiting Parallelism through High Level Optimization on a Heterogeneous Multicore SoCProceedings of the 2009 15th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2009.7(527-534)Online publication date: 8-Dec-2009
https://dl.acm.org/doi/10.1109/ICPADS.2009.7

Index Terms

Issues and challenges in compiling for the CBEA
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

June 2007

258 pages

ISBN:9781595936325

DOI:10.1145/1254766

General Chair:
Santosh Pande
Georgia Institute of Technology, USA
,
Program Chair:
Zhiyuan Li
Purdue University, USA

ACM SIGPLAN Notices Volume 42, Issue 7
Proceedings of the 2007 LCTES conference
July 2007
241 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1273444
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2007

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Conference

LCTES 07

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LCTES 07: ACM SIGBED-SIGPLAN Conference on Languages, Compilers and Tools for Embedded Systems

June 13 - 15, 2007

California, San Diego, USA

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Yan MZhao PYang ZLi S(2009)Exploiting Parallelism through High Level Optimization on a Heterogeneous Multicore SoCProceedings of the 2009 15th International Conference on Parallel and Distributed Systems10.1109/ICPADS.2009.7(527-534)Online publication date: 8-Dec-2009
https://dl.acm.org/doi/10.1109/ICPADS.2009.7

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