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Article

Soft error and energy consumption interactions: a data cache perspective

Authors:

Vijay Degalahal,

N. Vijaykrishnan,

Mahmut Kandemir,

Mary Jane IrwinAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 132 - 137

https://doi.org/10.1145/1013235.1013273

Published: 09 August 2004 Publication History

Abstract

Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the leakage optimization techniques can have very different reliability behavior as compared to an original cache with no leakage optimizations. Next, we investigate on providing data reliability in an energy efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.

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Cited By

Venkatesha SParthasarathi R(2024)Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and ReliabilityACM Computing Surveys10.1145/366367256:11(1-76)Online publication date: 6-May-2024
https://dl.acm.org/doi/10.1145/3663672
Zeng JZhang TJung C(2024)Compiler-Directed Whole-System Persistence2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00074(961-977)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00074
Zeng JJeong JJung C(2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623772
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Index Terms

Soft error and energy consumption interactions: a data cache perspective
1. Hardware
  1. Hardware test
  2. Robustness

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Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 August 2004

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ISLPED04

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ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Venkatesha SParthasarathi R(2024)Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators - Trends in Quantum Computing, Heterogeneous Systems and ReliabilityACM Computing Surveys10.1145/366367256:11(1-76)Online publication date: 6-May-2024
https://dl.acm.org/doi/10.1145/3663672
Zeng JZhang TJung C(2024)Compiler-Directed Whole-System Persistence2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00074(961-977)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00074
Zeng JJeong JJung C(2023)Persistent Processor ArchitectureProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623772(1075-1091)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3623772
Choi JZeng JLee DMin CJung CSolihin YHeinrich M(2023)Write-Light Cache for Energy Harvesting SystemsProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589098(1-13)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589098
Du XDong HZhang J(2022)MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under IrradiationIEEE Transactions on Nuclear Science10.1109/TNS.2022.315180569:5(1182-1192)Online publication date: May-2022
https://doi.org/10.1109/TNS.2022.3151805
Ko Y(2021)Characterizing System-Level Masking Effects against Soft ErrorsElectronics10.3390/electronics1018228610:18(2286)Online publication date: 17-Sep-2021
https://doi.org/10.3390/electronics10182286
Roy ALudwig S(2020)Recovery algorithm to correct silent data corruption of synaptic storage in convolutional neural networksInternational Journal of Hybrid Intelligent Systems10.3233/HIS-200278(1-11)Online publication date: 3-Aug-2020
https://doi.org/10.3233/HIS-200278
Farbeh HDelshadtehrani LKim HKim S(2020)ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache MemoriesIEEE Transactions on Computers10.1109/TC.2020.2994067(1-1)Online publication date: 2020
https://doi.org/10.1109/TC.2020.2994067
Venkatesha SParthasarathi R(2019)32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Â„Tolerant Core for Multicore SystemsJournal of Testing and Evaluation10.1520/JTE2018049247:6(20180492)Online publication date: 31-Jan-2019
https://doi.org/10.1520/JTE20180492
Prabakaran BDave MKriebel FRehman SShafique M(2019)Architectural-Space Exploration of Heterogeneous Reliability and Checkpointing Modes for Out-of-Order Superscalar ProcessorsIEEE Access10.1109/ACCESS.2019.29456227(145324-145339)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2019.2945622
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