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A generic micro-architectural test plan approach for microprocessor verification

Published: 13 June 2005 Publication History

Abstract

Modern microprocessors share several common types of micro-architectural building blocks. The rising complexity of the micro-architecture increases the risk of bugs and the difficulty of achieving comprehensive verification. We propose a methodology to exploit the commonality in the different microprocessors to create a design-independent micro-architectural test plan. Our method allows the testing of the huge micro-architectural test space by using systematic partitioning, which offers a high level of comprehensiveness of the tested behaviors. We show how this method was used to find bugs during verification of an actual high-end microprocessor. Our results show the advantages of this approach over the more traditional test methods that use design specific test plans or that use tools with little micro-architectural knowledge for covering micro-architectural aspects of the design.

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Cited By

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  • (2024)Aiding Microprocessor Performance Validation with Machine Learning2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00011(1-9)Online publication date: 5-May-2024
  • (2012)Cohesive Coverage ManagementJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5308-128:4(449-468)Online publication date: 1-Aug-2012
  • (2007)Automatic verification of external interrupt behaviors for microprocessor designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278701(896-901)Online publication date: 4-Jun-2007
  • Show More Cited By

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    cover image ACM Conferences
    DAC '05: Proceedings of the 42nd annual Design Automation Conference
    June 2005
    984 pages
    ISBN:1595930582
    DOI:10.1145/1065579
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 13 June 2005

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    Author Tags

    1. coverage
    2. dynamic verification
    3. generic test plan
    4. micro-architecture
    5. test generation

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    DAC05: The 42nd Annual Design Automation Conference 2005
    June 13 - 17, 2005
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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2024)Aiding Microprocessor Performance Validation with Machine Learning2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00011(1-9)Online publication date: 5-May-2024
    • (2012)Cohesive Coverage ManagementJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5308-128:4(449-468)Online publication date: 1-Aug-2012
    • (2007)Automatic verification of external interrupt behaviors for microprocessor designProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278701(896-901)Online publication date: 4-Jun-2007
    • (2006)Practical methods in coverage-oriented verification of the merom microprocessorProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146996(332-337)Online publication date: 24-Jul-2006
    • (2006)Advanced Analysis Techniques for Cross-Product CoverageIEEE Transactions on Computers10.1109/TC.2006.17355:11(1367-1379)Online publication date: 1-Nov-2006

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