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Power and performance tradeoffs using various caching strategies

Authors:

R. Iris Bahar,

Gianluca Albera,

Srilatha ManneAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 64 - 69

https://doi.org/10.1145/280756.295115

Published: 10 August 1998 Publication History

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Abstract

In this paper, we propose several different data and instruction cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several different power/performance sensitive cache configurations such as increasing cache size or associativity and including buffers along side L1 caches. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. As an alternative to simply increasing cache associativity or size to reduce lower-level memory energy consumption (which may have a detrimental effect on on-chip energy consumption), we show that, by using buffers, energy consumption of the memory subsystem may be reduced by as much as 13% for certain data cache configurations and by as much as 23% for certain instruction cache configurations without adversely effecting processor performance or on-chip energy consumption.

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Cited By

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Jindal NPanda PSarangi S(2018)Reusing Trace Buffers as Victim CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282792826:9(1699-1712)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2827928
Jindal NPanda PSarangi S(2017)Reusing trace buffers to enhance cache performanceProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130509(572-577)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130509
Jindal NPanda PSarangi S(2017)Reusing trace buffers to enhance cache performanceDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927052(572-577)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927052
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Power and performance tradeoffs using various caching strategies

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Published In

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

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ISLPED98

Sponsor:

IEEE-EDS
SIGDA
IEEE-SSCS
IEEE-CAS

ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Jindal NPanda PSarangi S(2018)Reusing Trace Buffers as Victim CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282792826:9(1699-1712)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2827928
Jindal NPanda PSarangi S(2017)Reusing trace buffers to enhance cache performanceProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130509(572-577)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130509
Jindal NPanda PSarangi S(2017)Reusing trace buffers to enhance cache performanceDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927052(572-577)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927052
Jhamb MSharma RGupta A(2017)A high level implementation and performance evaluation of level-I asynchronous cache on FPGAJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2015.06.00329:3(410-425)Online publication date: Jul-2017
https://doi.org/10.1016/j.jksuci.2015.06.003
Saravanan VPralhaddas KKothari DWoungang I(2015)An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUsHuman-centric Computing and Information Sciences10.1186/s13673-014-0016-85:1(1-13)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1186/s13673-014-0016-8
Gupta CBal B(2015)Detecting Sentiment in Nepali texts: A bootstrap approach for Sentiment Analysis of texts in the Nepali language2015 International Conference on Cognitive Computing and Information Processing(CCIP)10.1109/CCIP.2015.7100739(1-4)Online publication date: Mar-2015
https://doi.org/10.1109/CCIP.2015.7100739
Gupta AKaushal R(2015)Improving spam detection in Online Social Networks2015 International Conference on Cognitive Computing and Information Processing(CCIP)10.1109/CCIP.2015.7100738(1-6)Online publication date: Mar-2015
https://doi.org/10.1109/CCIP.2015.7100738
Gupta TVerma G(2015)Area & power optimization of VPB peripheral memory for ARM7TDMI based microcontrollers2015 International Conference on Cognitive Computing and Information Processing(CCIP)10.1109/CCIP.2015.7100716(1-6)Online publication date: Mar-2015
https://doi.org/10.1109/CCIP.2015.7100716
Paul A(2014)Real-Time Power Management for Embedded M2M Using Intelligent Learning MethodsACM Transactions on Embedded Computing Systems10.1145/263215813:5s(1-22)Online publication date: 23-Jul-2014
https://dl.acm.org/doi/10.1145/2632158
Alsafrjalani MRoss AViana P(2014)Minimum Effort Design Space Subsetting for Configurable CachesProceedings of the 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing10.1109/EUC.2014.19(65-72)Online publication date: 26-Aug-2014
https://dl.acm.org/doi/10.1109/EUC.2014.19
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SELECTIVE VICTIM CACHING: A METHOD TO IMPROVE THE PERFORMANCE OF DIRECT-MAPPED CACHES