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Inherent limitations on disjoint-access parallel implementations of transactional memory

Published: 11 August 2009 Publication History

Abstract

Transactional memory (TM) is a promising approach for designing concurrent data structures, and it is essential to develop better understanding of the formal properties that can be achieved by TM implementations. Two fundamental properties of TM implementations are disjoint-access parallelism, which is critical for their scalability, and the invisibility of read operations, which reduces memory contention.
This paper proves an inherent tradeoff for implementations of transactional memories: they cannot be both disjoint-access parallel and have read-only transactions that are invisible and always terminate successfully. In fact, a lower bound of Ω(t) is proved on the number of writes needed in order to implement a read-only transaction of t items, which successfully terminates in a disjoint-access parallel TM implementation. The results assume strict serializability and thus hold under the assumption of opacity. It is shown how to extend the results to hold also for weaker consistency conditions, serializability and snapshot isolation.

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cover image ACM Conferences
SPAA '09: Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
August 2009
370 pages
ISBN:9781605586069
DOI:10.1145/1583991
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 August 2009

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Author Tags

  1. disjoint-access parallelism
  2. impossibility result
  3. lower bound
  4. partial snapshots
  5. transactional memory

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Cited By

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  • (2020)An Overview of Hardware Implementation of Membrane Computing ModelsACM Computing Surveys10.1145/340245653:4(1-38)Online publication date: 3-Aug-2020
  • (2020)MeerkatProceedings of the Fifteenth European Conference on Computer Systems10.1145/3342195.3387529(1-14)Online publication date: 15-Apr-2020
  • (2018)The PCL TheoremJournal of the ACM10.1145/326614166:1(1-66)Online publication date: 12-Dec-2018
  • (2018)Boosting Transactional Memory with Stricter SerializabilityCoordination Models and Languages10.1007/978-3-319-92408-3_11(231-251)Online publication date: 27-May-2018
  • (2017)Scaling a file system to many cores using an operation logProceedings of the 26th Symposium on Operating Systems Principles10.1145/3132747.3132779(69-86)Online publication date: 14-Oct-2017
  • (2017)The scalable commutativity ruleCommunications of the ACM10.1145/306891460:8(83-90)Online publication date: 24-Jul-2017
  • (2017)Concurrency for the Masses: The Paradigm of Software Transactional Memory2017 19th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC)10.1109/SYNASC.2017.00012(17-22)Online publication date: Sep-2017
  • (2016)The SNOW theorem and latency-optimal read-only transactionsProceedings of the 12th USENIX conference on Operating Systems Design and Implementation10.5555/3026877.3026889(135-150)Online publication date: 2-Nov-2016
  • (2016)WFR-TMJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.05.00296:C(134-151)Online publication date: 1-Oct-2016
  • (2015)The Scalable Commutativity RuleACM Transactions on Computer Systems10.1145/269968132:4(1-47)Online publication date: 20-Jan-2015
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