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RTL c-based methodology for designing and verifying a multi-threaded processor

Published: 10 June 2002 Publication History

Abstract

A RTL C-Based design and verification methodology is presented with enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.

References

[1]
Avant! corp, Design Verifyer, http://www.avanticorp.com/
[2]
C Level Design, C2HDL, http://www.cleveldesign.com/
[3]
CoWare, N2C, http://coware.com/
[4]
Cynergy System Design, http://www.cynergysd.com

Cited By

View all
  • (2013)The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputersProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488884(1-9)Online publication date: 29-May-2013
  • (2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
  • (2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105403(679-686)Online publication date: 7-Nov-2011
  • Show More Cited By

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Published In

cover image ACM Conferences
DAC '02: Proceedings of the 39th annual Design Automation Conference
June 2002
956 pages
ISBN:1581134614
DOI:10.1145/513918
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

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Author Tags

  1. C/C++
  2. RTL
  3. checking
  4. design
  5. formal equivalence
  6. verification

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Conference

DAC02
Sponsor:
DAC02: 39th Design Automation Conference
June 10 - 14, 2002
Louisiana, New Orleans, USA

Acceptance Rates

DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

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Cited By

View all
  • (2013)The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputersProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488884(1-9)Online publication date: 29-May-2013
  • (2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
  • (2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105403(679-686)Online publication date: 7-Nov-2011
  • (2006)Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verificationProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147178(1063-1068)Online publication date: 24-Jul-2006
  • (2006)Automatic decomposition for sequential equivalence checking of system level and RTL descriptionsProceedings of the Fourth ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2006.1695903(71-80)Online publication date: 1-Jan-2006
  • (2005)Embedded tutorialProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129737(965-971)Online publication date: 31-May-2005
  • (2005)Partitioned model checking from software specificationsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120967(583-587)Online publication date: 18-Jan-2005
  • (2005)An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.60(30-31)Online publication date: 7-Mar-2005
  • (2004)MINCEProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969146Online publication date: 16-Feb-2004
  • (2004)Verification of SpecC using predicate abstractionProceedings of the Second ACM/IEEE International Conference on Formal Methods and Models for Co-Design10.1109/MEMCOD.2004.1459808(7-16)Online publication date: 1-Jan-2004
  • Show More Cited By

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