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Understanding co-run performance on CPU-GPU integrated processors: observations, insights, directions

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Abstract

Recent years have witnessed a processor development trend that integrates central processing unit (CPU) and graphic processing unit (GPU) into a single chip. The integration helps to save some host-device data copying that a discrete GPU usually requires, but also introduces deep resource sharing and possible interference between CPU and GPU. This work investigates the performance implications of independently co-running CPU and GPU programs on these platforms. First, we perform a comprehensive measurement that covers a wide variety of factors, including processor architectures, operating systems, benchmarks, timing mechanisms, inputs, and power management schemes. These measurements reveal a number of surprising observations.We analyze these observations and produce a list of novel insights, including the important roles of operating system (OS) context switching and power management in determining the program performance, and the subtle effect of CPU-GPU data copying. Finally, we confirm those insights through case studies, and point out some promising directions to mitigate anomalous performance degradation on integrated heterogeneous processors.

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Acknowledgements

We thank the constructive comments from the anonymous referees. This material was based upon work supported by DOE Early Career Award, the National Science Foundation (NSF) (1455404 and 1525609), and NSF CAREER Award. This work is also supported partly by the NSF (CNS-1217372, CNS-1239423, CCF-1255729, CNS-1319353, and CNS-1319417) and the National Natural Science Foundation of China (NSFC) (Grant Nos. 61272143, 61272144, and 61472431). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of DOE, NSF, or NSFC.

Author information

Authors and Affiliations

  1. National Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha, 410073, China

    Qi Zhu, Li Shen & Zhiying Wang

  2. Department of Computer Science, North Carolina State University, Raleigh, NC, 27695, USA

    Qi Zhu & Xipeng Shen

  3. Department of Electrical Engineering & Computer Science, Colorado School of Mines, Golden, CO, 80401, USA

    Bo Wu

  4. Department of Computer Science, University of Rochester, Rochester, NY, 14627, USA

    Kai Shen

Authors
  1. Qi Zhu
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  2. Bo Wu
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  3. Xipeng Shen
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  4. Kai Shen
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  5. Li Shen
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  6. Zhiying Wang
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Corresponding author

Correspondence to Qi Zhu.

Additional information

Qi Zhu, a doctoral candidate, received the MS degree in computer science from National University of Defense Technology, China in 2012. His research interests include compilers and programming systems, heterogeneous computing and emerging architectures.

Bo Wu, an assistant professor at Colorado School of Mines, USA, earned a PhD in computer science from the College of William and Mary, USA. His research lies in the broad field of compilers and programming systems, with an emphasis on program optimizations for heterogeneous computing and emerging architectures. His current focus is on high-performance graph analytics on GPUs and memory optimization for irregular applications.

Xipeng Shen is an associate professor at the Computer Science Department, North Carolina State University (NCSU), USA. He has been an IBM Canada Center for Advanced Studies (CAS) Research Faculty Fellow since 2010, and a receipt of the 2011 DOE Early Career Award and 2010 National Science Foundation (NSF) CAREER Award. His research lies in the broad field of programming systems, with an emphasis on enabling extreme-scale data-intensive computing and intelligent portable computing through innovations in both compilers and runtime systems. He has been particularly interested in capturing large-scale program behavior patterns, in both data accesses and code executions, and exploiting them for scalable and efficient computing in a heterogeneous, massively parallel environment. He leads the North Carolina State University-Compiler and Adaptive Programming Systems (NC-CAPS) research group.

Kai Shen is an associate professor at the Department of Computer Science, University of Rochester, USA. His research interests fall into the broad area of computer systems. Much of his work is driven by the complexity of modern computer systems and the need for principled approaches to understand, characterize, and manage such complexities. His is particularly interested in the cross-layer work of developing software system solution to support emerging hardware or address hardware issues, including the characterization and management of memory hardware errors, system support for flash-based SSDs and GPUs, as well as cyber-physical systems.

Li Shen received the BS, Master and PhD degrees in computer science and technology from the National University of Defense Technology (NUDT), China in 1997, 2000, and 2003, respectively. Currently, he is an associate professor of the School of Computer, NUDT. His research interests include programming model and compiler design, high performance processor architecture, virtualization technologies, and performance evaluation and workload characterization. He is a member of CCF and ACM.

Zhiying Wang received the PhD degree in electrical engineering from the National University of Defense Technology (NUDT), China in 1998. Currently, he is a professor of the School of Computer, NUDT. He has contributed over 10 invited chapters to book volumes, published 240 papers in archival journals and refereed conference proceedings, and delivered over 30 keynotes. His main research fields include computer architecture, computer security, very large scale integration (VLSI) design, reliable architecture, multicore memory system, and asynchronous circuit. He is a member of the CCF, ACM, and IEEE.

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Zhu, Q., Wu, B., Shen, X. et al. Understanding co-run performance on CPU-GPU integrated processors: observations, insights, directions. Front. Comput. Sci. 11, 130–146 (2017). https://doi.org/10.1007/s11704-016-5468-8

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  • DOI: https://doi.org/10.1007/s11704-016-5468-8

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