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Automated Design Flow for Multi-Functional Dataflow-Based Platforms

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Abstract

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.

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Notes

  1. The XML Dataflow Format (XDF) is an XML dialect, used to describe DPNs and standardized by MPEG [2].

  2. Please note that in [6] such a solution was named ”opt_reconfig”. Currently, the proposed design flow, on the basis of the high-level simulation results, allows to determine the optimal required buffering, therefore, we reserved the name opt for the design obtained by TURNUS with optimally sized buffers described above.

References

  1. Bhattacharyya, S.S., Eker, J., Janneck, J.W., Lucarz, C., Mattavelli, M., & Raulet, M. Overview of the mpeg reconfigurable video coding framework. Journal of Signal Processing Systems, 63(2).

  2. ISO/IEC 23001-4 (2009).MPEG systems tech.—Part 4: Codec configuration representation.

  3. Eker, J., & Janneck, J. CAL Language Report (ERL Technical Memo UCB/ERL M03/48).

  4. Carta, S., Pani, S., & Raffo, L. (2006). Reconfigurable coprocessor for multimedia application domain. Journal of VLSI Signal Processing Systems, 44(1-2), 135–152.

    Article  MATH  Google Scholar 

  5. Kumar, V., & Lach, J. (2006). Highly flexible multimode digital signal processing systems using adaptable components and controllers, EURASIP Jrnl. Applied Signal Proc.

  6. Sau, C., Raffo, L., Palumbo, F., Bezati, E., Casale-Brunet, S., & Mattavelli, M. (2014). Automated design flow for coarse-grained reconfigurable platforms: An rvc-cal multi-standard decoder use-case. In 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE (pp. 59–66).

  7. Dennis, J.B. (1974). First version of a data flow procedure language. In Symposium on Programming (pp. 362–376).

  8. Kahn, G. (1974). The semantics of simple language for parallel programming. In IFIP Congress (pp. 471–475).

  9. Lee, E.A., & Messerschmitt, D.G. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers, 36(1).

  10. Lee, E., & Parks, T. (1995). Dataflow process networks. Proceedings of the IEEE, 83(5), 773 –801.

    Article  Google Scholar 

  11. Casale-Brunet, S., Mattavelli, M., Elguindy, A., Bezati, E., Thavot, R., Roquier, G., & Janneck, J.. Methods to explore design space for MPEG RMC codec specifications, Jrnl. of Signal Proc. Image Communication: Elsevier.

  12. Dutt, N.D., & Mishra, P. Architecture description languages for programmable embedded systems. IEE Proc. Computers and Digital Techniques, 152(3).

  13. Rákossy, Z.E., Aponte, A.A., & Chattopadhyay, A. (2013). Exploiting architecture description language for diverse IP synthesis in heterogeneous mpsoc. In Conf. on Reconfigurable Computing and FPGAs (ReConFig) (pp. 1–6).

  14. Bezati, E., Casale-Brunet, S., Mattavelli, M., & Janneck, J. (2013). Synthesis and optimization of high-level stream programs. In Electronic System Level Synthesis Conf. (pp. 1–6).

  15. Wipliez, M., Siret, N., Carta, N., Palumbo, F., & Raffo, L. Design ip faster: Introducing the c high-level language, IP-SOC: IP-Embedded System Conference and Exhibition.

  16. Vivado design suite, http://www.xilinx.com/products/design-tools/vivado/.

  17. Automated generation of hardware accelerators with direct memory access from ansi/iso standard c functions, http://www.altera.com/support/ip/processors/nios2/ips-nios2_support.html.

  18. Schreiber, R., & et al. (2002). PICO-NPA: high-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 31(2), 127–142.

    Article  MATH  Google Scholar 

  19. Bond, B., Hammil, K., Litchev, L., & Singh, S. (2010). FPGA circuit synthesis of accelerator data-parallel programs. In 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE. doi:10.1109/FCCM.2010.51.

  20. Rutten, M.J., Gangwal, O.P., van Eijndhoven, J.T.J., Jaspers, E.G.T., & Pol, E.D. (2004). Application design trajectory towards reusable coprocessors MPEG case study. In Proceedings of the 2002 2nd Workshop on Embedded Systems for Real-Time Multimedia, ESTImedia 2004, September 6-7, Stockholm, Sweden (pp. 33–38).

  21. Oh, H., & Ha, S. (1999). A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling. In Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999. doi:10.1145/301177.301524 (pp. 183–187).

  22. Kumar, A., Fernando, S., Ha, Y., Mesman, B., & Corporaal, H. Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Transactions on Design Automation of Electronic Systems, 13(3). doi:10.1145/1367045.1367049.

  23. Wildermann, S., Reimann, F., Ziener, D., & Teich, J. (2013). Symbolic system-level design methodology for multi-mode reconfigurable systems. Design Automation for Embedded Systems, 17(2), 343–375. doi:10.1007/s10617-012-9102-1.

    Article  Google Scholar 

  24. Open rvc-cal compiler (orcc), http://orcc.sourceforge.net/.

  25. Palumbo, F., Pani, D., Manca, E., Raffo, L., Mattavelli, M., & Roquier, G. (2010). Rvc: A multi-decoder cal composer tool. In Conf. on Design and Architectures for Signal and Image Proc. (pp. 144–151).

  26. Palumbo, F., Carta, N., & Raffo, L. (2011). The multi-dataflow composer tool: A runtime reconfigurable hdl platform composer. In Conf. on Design and Architectures for Signal and Image Proc. (pp. 178–185).

  27. Palumbo, F., Carta, N., Pani, D., & Meloni, P. (2012). The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms, Jrnl. of Real-Time Image Proc. doi:10.1007/s11554-012-0284-3.

  28. Casale-Brunet, S., Mattavelli, M., & Janneck, J. (2013). Buffer optimization based on critical path analysis of a dataflow program design. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS.2013.6572113 (pp. 1384–1387).

  29. TURNUS, http://www.turnus.co and http://github.com/turnus (Last checked: October 2014).

  30. Casale-Brunet, S., Alberti, C., Mattavelli, M., & Janneck, J. Turnus: a unified dataflow design space exploration framework for heterogeneous parallel systems. In 2013 Conference on Design and Archtictures for Signal and Image Processing (DASIP), Cagliari, Italy.

  31. Janneck, J., Miller, I., & Parlour, D. (2008). Profiling dataflow programs. In Proceedings of the IEEE International Conf. on Multimedia and Expo (pp. 1065–1068).

  32. Ravasi, M., & Mattavelli, M. (2005). High-abstraction level complexity analysis and memory architecture simulations of multimedia algorithms. IEEE Transactions on Circuits and Systems for Video Technology, 15(5), 673–684.

    Article  Google Scholar 

  33. Casale-Brunet, S., Mattavelli, M., & Janneck, J. (2012). Profiling of dataflow programs using post mortem causation traces. In 2012 IEEE Workshop on Signal Processing Systems (SiPS) (pp. 220–225).

  34. Bhattacharyya, S., Deprettere, E., & Theelen, B. (2013). Dynamic dataflow graphs. In Handbook of Signal Processing Systems (pp. 905–944): Springer.

  35. K. Ravindran. Task allocation and scheduling of concurrent applications to multiprocessor systems, Ph.D. thesis, EECS Department, University of California, Berkeley (Dec 2007).

  36. Gross, J., & Yellen, J. (2005). Graph theory and its applications, Second Edition (Discrete mathematics and its applications): Chapman & Hall/CRC.

  37. Brunet, S.C., Bezati, E., Mattavelli, M., Canale, M., & Janneck, J.W. (2014). Execution trace graph analysis of dataflow programs: bounded buffer scheduling and deadlock recovery using model predictive control. In 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, October, 2014.

  38. Rahman, A.A.H.A, Brunet, S.C., Alberti, C., & Mattavelli, M. (2014). A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations. In IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2014, Florence, Italy, May 4-9, 2014. doi:10.1109/ICASSP.2014.6854554(pp. 5003–5007).

  39. Janneck, J., Miller, I., Parlour, D., Roquier, G., Wipliez, M., & Raulet, M. Synthesizing hardware from dataflow programs: an MPEG-4 simple profile decoder case study. Journal of Signal Processing Systems, 63(2), 241–249.

  40. Palumbo, F., Sau, C., & Raffo, L. (2013). Dse and profiling of multi-context coarse-grained reconfigurable systems. In 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA), IEEE (pp. 744–749).

  41. Independent jpeg group, http://www.ijg.org/.

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Authors and Affiliations

  1. Universitá degli studi di Cagliari, IT, Cagliari, Italy

    Carlo Sau, Paolo Meloni & Luigi Raffo

  2. Universitá degli studi di Sassari, IT, Sassari, Italy

    Francesca Palumbo

  3. École Polytechnique Fédérale de Lausanne, CH, Lausanne, Switzerland

    Endri Bezati, Simone Casale-Brunet & Marco Mattavelli

Authors
  1. Carlo Sau
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  2. Paolo Meloni
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  3. Luigi Raffo
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  4. Francesca Palumbo
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  6. Simone Casale-Brunet
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  7. Marco Mattavelli
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Correspondence to Carlo Sau.

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Sau, C., Meloni, P., Raffo, L. et al. Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J Sign Process Syst 85, 143–165 (2016). https://doi.org/10.1007/s11265-015-1026-0

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