Abstract
The latency, bandwidth, and power consumption of on-chip interconnection networks are central concerns in the design of multi- and many-core microprocessors. When the global network-on-chip (NoC) is electrical, the power consumption and the limited connectivity caused by difficulties associated with global wires will limit network performance due to power or topology constraints unless applications can be written, which only require nearest neighbor communication. This is a highly unlikely scenario, and these performance and power barriers will become more severe with shrinking process technology and increased core counts. Emerging CMOS nanophotonic technologies provide a compelling alternative to traditional all-electronic NoCs. Wire power consumption is fundamentally linear with wire length. Due to the low loss nature of waveguides, optical data transmission primarily consumes energy at the endpoints where optical to electrical (OE) and electrical to optical (EO) conversion takes place. Therefore, the energy required to transport data is relatively independent of path length for path lengths of interest for NoC-based systems. Additionally, the use of wave division multiplexing can be exploited to improve per lane bandwidth. Signal integrity limitations make this option intractable for electrical NoCs. The result is that nanophotonic NoCs can provide both higher throughput and lower power consumption than all-electrical NoCs. This chapter introduces CMOS nanophotonic technology and considers its use in photonic chip-wide networks enabling many-core microprocessors with greatly enhanced performance and flexibility while consuming less power than their electrical counterparts. It provides, as a case study, a design that takes advantage of CMOS nanophotonics to achieve ten-teraop performance in a 256-core 3D chip stack, using optically connected main memory, very high memory bandwidth, cache coherence across all cores, no bisection bandwidth limits on communication, and cross-chip communication at very low latency with cache-line granularity.
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Ahn, J.H. et al. (2011). CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_9
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