Abstract
This paper studies the buffer planning problem for interconnect centric floorplanning. Dead-spaces not held by blocks are the available location for buffer insertion. To make best use of these spaces for buffer requirements, we have to move blocks so that blocks’ room size is adjusted and dead-spaces could be redistributed. In this paper, we introduce a new algorithm to move blocks not only within its room, but also in the space currently held by other blocks by pushing away these blocks if necessary without violating the topological and the total area. After applying this method of redistributing dead-spaces, the number of nets satisfying delay constraint can be optimized.
This paper is supported by National Nature Science Foundation of China (NSFC): 60473126, NSFC 60121120706 and National Natural Science Foundation of USA (NSF) CCR-0096383, Hi-Tech Research & Development (863) Program of China 2004AA1Z1050
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Hong, X.L., Dong, S., Huang, G., et al.: Corner block list representation and its application to floorplan optimization. IEEE Trans. on Circuits and Systems II: Express Briefs 51(5), 228–233 (2004)
Chen, S., Hong, X.L., Dong, S.Q., Ma, Y.C.: A buffer planning algorithm based on dead space redistributio. In: ASP-DAC (2003)
Cong, J., Kong, T., Pan, D.Z.: Buffer block planning for interconnect-driven floorplanning. In: IEEE/ACM ICCAD (1999)
Ma, Y.C., Hong, X.L., Dong, S.Q., Chen, S., Cai, Y.C.: An Integrated Floorplanning with an Efficient Buffer Planning Algorithm. In: ISPD (2003)
Sarkar, P., Koh, C.K.: Routability-driven repeater block planning for interconnect-centric floorplanning. In: ISPD (2000)
Tang, X., Wong, D.F.: Planning buffer locations by network flows. In: Intl. Symp. Physical Design, pp. 180–185 (2000)
Dragan, F.F., Kahng, A.B., et al.: Provably good global buffering by multiterminal multicommodity flow approximation. In: ASP-DAC (2001)
Sham, C.W., Young, F.Y.: Routability driven floorplanner with buffer block planning. In: ISPD (2002)
Ragiq, F., Jeske, M.C., Yang, H.H., Sherwani, N.: Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. In: ISPD (2002)
Alpert, C.J., Devgan, A.: Wire segmenting for improved buffer insertion. In: Proc. Design Automation Conf., June 1997, pp. 588–593 (1997)
Semiconductor Industry Association, National Technology Roadmap for Semiconductors (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bai, H., Dong, S., Hong, X., Chen, S. (2005). A New Buffer Planning Algorithm Based on Room Resizing. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_31
Download citation
DOI: https://doi.org/10.1007/11596356_31
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)