Abstract
Contemporary superscalar processors, designed with a one-size-fits-all philosophy, grossly overcommit significant portions of datapath resources that remain unnecessarily activated in the course of program execution. We present a simple scheme for selectively activating regions within the register file and the reorder buffer for reducing leakage as well as dynamic power dissipation. Our techniques result in power savings in excess of 60% in these components, on the average with no performance loss.
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© 2005 Springer-Verlag Berlin Heidelberg
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Khasawneh, S.T., Ghose, K. (2005). An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_51
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DOI: https://doi.org/10.1007/11556930_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
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