• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 32 matches

• 2023
• 
  Subhendu Ruidas, Mijanur Rahaman Seikh, Prasun Kumar Nayak, Ming-Lang Tseng:
  An interval-valued green production inventory model under controllable carbon emissions and green subsidy via particle swarm optimization. Soft Comput. 27(14): 9709-9733 (2023)
• 2022
• 
  Subhendu Ruidas, Mijanur Rahaman Seikh, Prasun Kumar Nayak:
  A production-repairing inventory model considering demand and the proportion of defective items as rough intervals. Oper. Res. 22(3): 2803-2829 (2022)
• 
  Munshi Mostafijur Rahaman, Prasun Ghosal, Chandan Giri:
  WiZ-BMS: A Hybrid Wireless Network-on-Chip Design with Fully Adaptive Routing. iSES 2022: 242-247
• 2021
• 
  Subhendu Ruidas, Mijanur Rahaman Seikh, Prasun Kumar Nayak:
  A production inventory model with interval-valued carbon emission parameters under price-sensitive demand. Comput. Ind. Eng. 154: 107154 (2021)
• 
  Mijanur Rahaman Seikh, Shuvasree Karmakar, Prasun Kumar Nayak:
  Matrix games with dense fuzzy payoffs. Int. J. Intell. Syst. 36(4): 1770-1799 (2021)
• 2020
• 
  Subhendu Ruidas, Mijanur Rahaman Seikh, Prasun Kumar Nayak:
  An EPQ model with stock and selling price dependent demand and variable production rate in interval environment. Int. J. Syst. Assur. Eng. Manag. 11(2): 385-399 (2020)
• 
  Prasun K. Raha, Tomai Knopp, Sagheer Ahmad, Ahmad Ansari, Fu-Hing Ho, Thomas To, Vamsi Nalluri, Mrinal Sarmah, Rajeev Patwari:
  8.2 A Versatile 7nm Adaptive Compute Acceleration Platform Processor. ISSCC 2020: 146-148
• 2019
• 
  Munshi Mostafijur Rahaman, Prasun Ghosal, Tuhin Subhra Das:
  Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region. J. Circuits Syst. Comput. 28(4): 1950055:1-1950055:21 (2019)
• 2016
• 
  Soumyajit Poddar, Prasun Ghosal, Hafizur Rahaman:
  Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip. ACM Trans. Embed. Comput. Syst. 15(1): 2:1-2:30 (2016)
• 
  Munshi Mostafijur Rahaman, Prasun Ghosal, Siddhartha Biswas:
  A Scalable Hierarchical Ring Based Wireless Network-on-Chip. ICIT 2016: 154-159
• 2015
• 
  Sibasis Bandyopadhyay, Swapan Raha, Prasun Kumar Nayak:
  Matrix Game with Z-numbers. Int. J. Fuzzy Log. Intell. Syst. 15(1): 60-71 (2015)
• 
  Soumyajit Poddar, Prasun Ghosal, Hafizur Rahaman:
  Adaptive CDMA based multicast method for photonic networks on chip. SoCC 2015: 298-303
• 2014
• 
  Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman:
  An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects. VLSID 2014: 433-438
• 2013
• 
  Mijanur Rahaman Seikh, Prasun Kumar Nayak, Madhumangal Pal:
  Notes on triangular intuitionistic fuzzy numbers. Int. J. Math. Oper. Res. 5(4): 446-465 (2013)
• 
  Mijanur Rahaman Seikh, Prasun Kumar Nayak, Madhumangal Pal:
  Matrix games in intuitionistic fuzzy environment. Int. J. Math. Oper. Res. 5(6): 693-708 (2013)
• 
  Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
  An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip. ISED 2013: 113-117
• 2012
• 
  Prasun Ghosal, Sunita Choudhuri, Hafizur Rahaman:
  Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach. HPCC-ICESS 2012: 532-537
• 
  Manodipan Sahoo, Prasun Ghosal, Hafizur Rahaman:
  Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects. ISED 2012: 236-240
• 
  Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
  Design of an NoC with on-chip photonic interconnects using adaptive CDMA links. SoCC 2012: 352-357
• 
  Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
  A Photonic Network on Chip with CDMA Links. VDAT 2012: 377-378
• 2011
• 
  Prasun Ghosal, Hafizur Rahaman, Satrajit Das, Arindam Das, Parthasarathi Dasgupta:
  Obstacle Aware Routing in 3D Integrated Circuits. ADCONS 2011: 451-460
• 2010
• 
  Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
  Minimizing Thermal Disparities during Placement in 3D ICs. CSE 2010: 160-167
• 2009
• 
  Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta:
  A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. VLSI Design 2009: 387-392
• 2008
• 
  Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
  Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. ISVLSI 2008: 369-374
• 
  Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
  Revisiting fidelity: a case of elmore-based Y-routing trees. SLIP 2008: 27-34
• 2007
• 
  Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
  Minimum-Congestion Placement for Y-interconnects: Some studies and observations. ISVLSI 2007: 73-80
• 2006
• 
  Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
  A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. ISCAS 2006
• 2005
• 
  Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
  Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. IICAI 2005: 232-251
• 2004
• 
  Vishal Gupta, Gabriel A. Rincón-Mora, Prasun Raha:
  Analysis and design of monolithic, high PSR, linear regulators for SoC applications. SoCC 2004: 311-315
• 2002
• 
  Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun:
  A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-153

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