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"A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled ..."

Chua-Chin Wang et al. (2008)

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DOI: 10.1142/S0218126608004708

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - journals/jcsc/WangSHLCLH08
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  - https://dblp.org/rec/journals/jcsc/WangSHLCLH08
Chua-Chin Wang, Gang-Neng Sung, Chi-Chun Huang, Ching-Li Lee, Tian-Hau Chen, Wun-Ji Lin, Ron Hu:
A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. J. Circuits Syst. Comput. 17(5): 943-956 (2008)

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