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"Low Power, High Speed and Area Efficient Binary Count Multiplier."

Kore Sagar Dattatraya et al. (2016)

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DOI: 10.1142/S0218126616500274

access: closed

type: Journal Article

metadata version: 2020-08-25

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  - journals/jcsc/DattatrayaBKB16
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  - https://dblp.org/rec/journals/jcsc/DattatrayaBKB16
Kore Sagar Dattatraya, Ritesh Belgudri, Ramdas Bhanudas Khaladkar, V. S. Kanchana Bhaaskaran:
Low Power, High Speed and Area Efficient Binary Count Multiplier. J. Circuits Syst. Comput. 25(4): 1650027:1-1650027:17 (2016)

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