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"Approximating complex arithmetic circuits with formal error guarantees: ..."

Milan Ceska et al. (2017)

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DOI: 10.1109/ICCAD.2017.8203807

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/iccad/CeskaMMSVV17
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  persistent URL:
  - https://dblp.org/rec/conf/iccad/CeskaMMSVV17
Milan Ceska, Jirí Matyás, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar:
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. ICCAD 2017: 416-423

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