2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.">2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET., dblp, computer science, bibliography, knowledge graph, author, editor, publication, conference, journal, book, thesis, database, collection, open data, bibtex">

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"DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit ..."

Fei Gao et al. (2023)

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DOI: 10.1109/CICC57935.2023.10121257

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-13

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Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff:
DECADES: A 67mm², 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. CICC 2023: 1-2

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