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"A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet ..."

Rakshith Saligram et al. (2020)

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DOI: 10.1109/VLSI-SOC46417.2020.9344081

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-17

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  - conf/vlsi/SaligramKBR20
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Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury:
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. VLSI-SOC 2020: 159-164

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