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Anne-Johan Annema
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- affiliation: University of Twente, Enschede, Netherlands
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2020 – today
- 2023
- [j23]Alexander S. Delke
, Thomas J. Hoen
A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz. IEEE J. Solid State Circuits 58(9): 2585-2596 (2023) - 2022
- [j22]Maikel Huiskamp
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 999-1012 (2022) - 2021
- [j21]Alexander S. Delke
A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C. IEEE J. Solid State Circuits 56(11): 3434-3444 (2021) - 2020
- [j20]Jeroen Ponte
Theory and Implementation of a Load-Mismatch Protective Class-E PA System. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 369-377 (2020) - [c23]Alexander S. Delke, Anne-Johan Annema, Mark S. Oude Alink
A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C. CICC 2020: 1-4
2010 – 2019
- 2019
- [j19]Ali Ghahremani
A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1149-1153 (2019) - [c22]Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC 2019: 1-4 - [c21]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits 2019: 74- - 2018
- [j18]Ali Ghahremani
Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement. IEEE J. Solid State Circuits 53(5): 1374-1386 (2018) - [j17]Harijot Singh Bindra
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53(7): 1902-1912 (2018) - [j16]Maikel Huiskamp
A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1834-1838 (2018) - [c20]Jeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta
Augmentation of Class-E PA Reliability under Load Mismatch Conditions. ICECS 2018: 33-36 - 2017
- [j15]Ettore Lorenzo Firrao, Anne-Johan Annema, Frank E. van Vliet, Bram Nauta
Hardware Implementation Overhead of Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1152-1163 (2017) - [c19]Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC 2017: 217-220 - [c18]Harijot Singh Bindra, Chris E. Lokin
A 30fJ/comparison dynamic bias comparator. ESSCIRC 2017: 71-74 - [c17]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC 2017: 235-238 - 2016
- [c16]Vishal Agarwal, Anne-Johan Annema, Satadal Dutta
Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs. ESSDERC 2016: 264-267 - 2015
- [j14]Erik Olieman, Anne-Johan Annema
An Interleaved Full Nyquist High-Speed DAC Technique. IEEE J. Solid State Circuits 50(3): 704-713 (2015) - [j13]Ettore Lorenzo Firrao, Anne-Johan Annema
On the Minimum Number of States for Switchable Matching Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 433-440 (2015) - 2014
- [c15]Erik Olieman, Anne-Johan Annema
A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. VLSIC 2014: 1-2 - 2013
- [j12]Wei Cheng, Mark S. Oude Alink
A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators. IEEE J. Solid State Circuits 48(2): 358-368 (2013) - [j11]Wei Cheng, Anne-Johan Annema
A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance. IEEE J. Solid State Circuits 48(10): 2390-2402 (2013) - 2012
- [j10]Wei Cheng, Mark S. Oude Alink
RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2340-2353 (2012) - [c14]Benaoumeur Senouci, Anne-Johan Annema
Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design. DSD 2012: 837-843 - [c13]Wei Cheng, Mark S. Oude Alink
A wideband IM3 cancellation technique for CMOS attenuators. ISSCC 2012: 78-80 - [c12]Anne-Johan Annema
A 0.0025mm2 bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS. ISSCC 2012: 364-366 - 2011
- [j9]Wei Cheng, Anne-Johan Annema
Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 276-289 (2011)
2000 – 2009
- 2009
- [c11]Paul Veldhorst, George Goksun, Anne-Johan Annema
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. ESSCIRC 2009: 464-467 - [c10]Anne-Johan Annema
A sub-1V bandgap voltage reference in 32nm FinFET technology. ISSCC 2009: 332-333 - 2008
- [c9]Wei Cheng, Anne-Johan Annema
A general weak nonlinearity model for LNAs. CICC 2008: 221-224 - [c8]Wei Cheng, Anne-Johan Annema
A multi-step P-cell for LNA design automation. ISCAS 2008: 2550-2553 - [c7]Mustafa Acar, Anne-Johan Annema
Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology. ISSCC 2008: 530-531 - 2007
- [j8]Mustafa Acar, Anne-Johan Annema
Analytical Design Equations for Class-E Power Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2706-2717 (2007) - [c6]Mustafa Acar, Anne-Johan Annema, Bram Nauta:
Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. ISCAS 2007: 2818-2821 - 2006
- [c5]Mustafa Acar, Anne-Johan Annema
Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers. ICECS 2006: 431-434 - 2005
- [j7]Anne-Johan Annema
Analog circuits in ultra-deep-submicron CMOS. IEEE J. Solid State Circuits 40(1): 132-143 (2005) - [j6]Sasa Radovanovic, Anne-Johan Annema
A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication. IEEE J. Solid State Circuits 40(8): 1706-1717 (2005) - [j5]Sasa Radovanovic, Anne-Johan Annema, Bram Nauta
Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications. Microelectron. Reliab. 45(3-4): 705-710 (2005) - [c4]Bram Nauta
Analog/RF circuit design techniques for nanometerscale IC technologies. ESSCIRC 2005: 45-53 - [c3]T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema
An audio FIR-DAC in a BCD process for high power class-D amplifiers. ESSCIRC 2005: 459-462 - 2004
- [c2]Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema:
Reducing quantization noise with recursive Sigma Delta modulators. ISCAS (1) 2004: 1084-1087 - 2001
- [j4]Anne-Johan Annema, Govert J. G. M. Geelen, Peter C. de Jong:
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. IEEE J. Solid State Circuits 36(3): 528-538 (2001) - 2000
- [c1]Anne-Johan Annema, Govert Geelen, Peter C. de Jong:
5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. CICC 2000: 417-420
1990 – 1999
- 1999
- [j3]Anne-Johan Annema
Low-power bandgap references featuring DTMOSTs. IEEE J. Solid State Circuits 34(7): 949-955 (1999) - 1995
- [b1]Anne-Johan Annema:
Feed-forward neural networks - vector decomposition analysis, modelling and analog implementation. The Kluwer international series in engineering and computer science 314, Kluwer 1995, ISBN 978-0-7923-9567-6, pp. I-XIII, 1-238 - [j2]Anne-Johan Annema, Hans Wallinga:
Analog weight adaptation hardware. Neural Process. Lett. 2(3): 7-11 (1995) - 1994
- [j1]Anne-Johan Annema
Learning behavior and temporary minima of two-layer neural networks. Neural Networks 7(9): 1387-1404 (1994)
Coauthor Index
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