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Chi-Li Yu
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2010 – 2019
- 2013
- [j3]Ahmed Al-Maashri
, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Chi-Li Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
Hardware Acceleration for Neuromorphic Vision Algorithms. J. Signal Process. Syst. 70(2): 163-175 (2013) - 2012
- [b1]Chi-Li Yu:
Multidimensional DFT IP Generators for FPGA Platforms. Arizona State University, Tempe, USA, 2012 - [c10]Chi-Li Yu, Chaitali Chakrabarti:
Transpose-free SAR imaging on FPGA platform. ISCAS 2012: 762-765 - 2011
- [j2]Chi-Li Yu, Kevin M. Irick, Chaitali Chakrabarti, Vijaykrishnan Narayanan:
Multidimensional DFT IP Generator for FPGA Platforms. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 755-764 (2011) - [j1]Chi-Li Yu, Jungsub Kim, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. J. Signal Process. Syst. 64(1): 109-122 (2011) - [c9]Michael DeBole, Yang Xiao, Chi-Li Yu, Ahmed Al-Maashri
FPGA-accelerator system for computing biologically inspired feature extraction models. ACSCC 2011: 751-755 - [c8]Michael DeBole, Ahmed Al-Maashri
A framework for accelerating neuromorphic-vision algorithms on FPGAs. ICCAD 2011: 810-813 - [c7]Ahmed Al-Maashri
A hardware architecture for accelerating neuromorphic vision algorithms. SiPS 2011: 355-360 - 2010
- [c6]Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vijaykrishnan Narayanan:
Bandwidth-intensive FPGA architecture for multi-dimensional DFT. ICASSP 2010: 1486-1489
2000 – 2009
- 2009
- [c5]Jungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti:
FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. SiPS 2009: 121-126 - 2008
- [c4]Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan:
Efficient image reconstruction using partial 2D Fourier transform. SiPS 2008: 49-54 - 2007
- [c3]Chi-Li Yu, Tzu-Hao Yu, An-Yeu Wu
On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm. SiPS 2007: 430-435 - 2006
- [c2]Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. SiPS 2006: 422-427 - 2001
- [c1]Chi-Li Yu, An-Yeu Wu
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. ISCAS (4) 2001: 250-253
Coauthor Index
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