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Anup Dandapat
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2020 – today
- 2024
- [j24]Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat:
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine. Integr. 98: 102213 (2024) - 2023
- [j23]Sheikh Wasmir Hussain
, Telajala Venkata Mahendra, Sandeep Mishra
SMS-CAM: Shared matchline scheme for content addressable memory. Integr. 88: 70-79 (2023) - 2022
- [j22]Keshab Das, Anup Dandapat
Design of a 1.29-1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation. J. Circuits Syst. Comput. 31(16): 2250274:1-2250274:16 (2022) - 2021
- [j21]Sheikh Wasmir Hussain
Match-line control unit for power and delay reduction in hybrid CAM. IET Circuits Devices Syst. 15(3): 272-283 (2021) - 2020
- [j20]Sandeep Mishra
The analogy of matchline sensing techniques for content addressable memory (CAM). IET Comput. Digit. Tech. 14(3): 87-96 (2020) - [j19]Sheikh Wasmir Hussain, Telajala Venkata Mahendra
Low-power content addressable memory design using two-layer P-N match-line control and sensing. Integr. 75: 73-84 (2020) - [j18]Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat:
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM). J. Inf. Sci. Eng. 36(5): 1035-1053 (2020) - [j17]Telajala Venkata Mahendra
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2345-2357 (2020)
2010 – 2019
- 2019
- [j16]Telajala Venkata Mahendra
Low discharge precharge free matchline structure for energy-efficient search using CAM. Integr. 69: 31-39 (2019) - [c5]Telajala Venkata Mahendra
A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory. iSES 2019: 369-372 - 2018
- [j15]Sandeep Mishra
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1591-1601 (2018) - [j14]Sheikh Wasmir Hussain
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory. IEEE Trans. Consumer Electron. 64(3): 301-309 (2018) - 2017
- [j13]Sandeep Mishra
Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 710-714 (2017) - [j12]Telajala Venkata Mahendra
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2388-2392 (2017) - [c4]Venkatesh Mani Tripathi, Sandeep Mishra
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. VLSID 2017: 341-346 - 2016
- [j11]Vinay Kumar
Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique. J. Circuits Syst. Comput. 25(12): 1650153:1-1650153:20 (2016) - [j10]Vinay Kumar
A Novel Methodology for Design of Cyclic Combinational Circuits. J. Low Power Electron. 12(3): 205-217 (2016) - [j9]Sandeep Mishra
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1910-1920 (2016) - [j8]Sandeep Mishra
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2142-2151 (2016) - 2015
- [j7]Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2001-2008 (2015) - 2014
- [j6]Prabir Saha
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8(1): 27-37 (2014) - [j5]Prabir Saha
Design of 64-Bit Squarer Based on Vedic Mathematics. J. Circuits Syst. Comput. 23(7) (2014) - [j4]D. Kayal, Posiba Mostafa, Anup Dandapat
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique. J. Signal Process. Syst. 76(1): 1-9 (2014) - 2013
- [j3]D. Ghosh, P. C. Mondal, D. Kayal, Partha Bhattacharyya, Anup Dandapat
A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique. J. Low Power Electron. 9(4): 421-426 (2013) - [c3]Prabir Saha
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. ISED 2013: 41-45 - 2012
- [c2]Prabir Saha
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT 2012: 79-88 - 2011
- [j2]Prabir Saha
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42(12): 1343-1352 (2011) - [c1]Prabir Saha
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED 2011: 67-71
2000 – 2009
- 2008
- [j1]Anup Dandapat
Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM. J. Low Power Electron. 4(2): 158-168 (2008)
Coauthor Index
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