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Dong-Young Chang
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2010 – 2019
- 2017
- [c6]Ayman Shabra, Dong-Young Chang:
Session 7 - Data converter techniques. CICC 2017: 1 - 2014
- [j10]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. IEEE J. Solid State Circuits 49(6): 1366-1382 (2014) - [c5]Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer:
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. ISSCC 2014: 204-205 - 2012
- [c4]Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer:
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. CICC 2012: 1-4
2000 – 2009
- 2008
- [j9]Alfio Zanchi, Dong-Young Chang:
A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2166-2177 (2008) - 2005
- [j8]Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon:
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. IEEE J. Solid State Circuits 40(4): 960-969 (2005) - [j7]Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon:
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. IEEE J. Solid State Circuits 40(12): 2398-2407 (2005) - [j6]Dong-Young Chang, Gil-Cho Ahn, Un-Ku Moon:
Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 1-12 (2005) - [j5]Brandon Greenley, Raymond Veith, Dong-Young Chang, Un-Ku Moon:
A low-Voltage 10-bit CMOS DAC in 0.01-mm2 die area. IEEE Trans. Circuits Syst. II Express Briefs 52-II(5): 246-250 (2005) - 2004
- [j4]Dong-Young Chang:
Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(11): 2123-2132 (2004) - [j3]Dong-Young Chang, Jipeng Li, Un-Ku Moon:
Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(11): 2133-2140 (2004) - 2003
- [j2]Dong-Young Chang, Un-Ku Moon:
A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique. IEEE J. Solid State Circuits 38(8): 1401-1404 (2003) - 2002
- [c3]Dong-Young Chang, Lei Wu, Un-Ku Moon:
Low-voltage pipelined ADC using opamp-reset switching technique. CICC 2002: 461-464
1990 – 1999
- 1999
- [c2]Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee:
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. ASP-DAC 1999: 45-48 - [c1]Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee:
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. ASP-DAC 1999: 273 - 1998
- [j1]Dong-Young Chang, Seung-Hoon Lee:
Design techniques for a low-power low-cost CMOS A/D converter. IEEE J. Solid State Circuits 33(8): 1244-1248 (1998)
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