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Naoya Watanabe
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2020 – today
- 2021
- [j12]Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata
, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18(9): 20210070 (2021) - [j11]Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18(11): 20210139 (2021) - 2020
- [j10]Takuji Miki
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020)
2010 – 2019
- 2019
- [c17]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC 2019: 1-4 - [c16]Takuji Miki, Makoto Nagata
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c15]Takuji Miki, Makoto Nagata
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - 2017
- [j9]Samson Melamed
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79: 380-386 (2017) - 2016
- [j8]Wei Feng, Naoya Watanabe
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59: 95-101 (2016) - [j7]Wei Feng, Tung Thanh Bui
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63: 142-147 (2016) - [j6]Samson Melamed
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67: 2-8 (2016) - [c14]Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura:
Wet cleaning process for high-yield via-last TSV formation. 3DIC 2016: 1-4 - 2015
- [c13]Tung Thanh Bui
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC 2015: TS8.6.1-TS8.6.4 - 2014
- [c12]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Analysis of thermal stress distribution for TSV with novel structure. 3DIC 2014: 1-4 - [c11]Bui Thanh Tung
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC 2014: 1-4 - [c10]Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto:
Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 3DIC 2014: 1-5 - [c9]Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi:
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. ISSCC 2014: 240-241 - 2013
- [j5]Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai:
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. IEEE J. Solid State Circuits 48(11): 2671-2680 (2013) - [c8]Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi:
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC 2013: 1-5 - 2011
- [c7]Akihiro Ikeda, Naoya Watanabe, Tanemasa Asano:
High frequency signal transmission characteristics of cone bump interconnections. 3DIC 2011: 1-5 - [c6]Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka:
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC 2011: 1-4 - [c5]Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, Tanemasa Asano:
Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration. 3DIC 2011: 1-4 - [c4]Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa:
Damage evaluation of wet-chemical silicon-wafer thinning process. 3DIC 2011: 1-4
2000 – 2009
- 2005
- [j4]Akira Yamazaki, Fukashi Morishita
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. 88-C(10): 2020-2027 (2005)
1990 – 1999
- 1999
- [j3]Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999) - 1996
- [j2]Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya:
A 90-MHz 16-Mb system integrated memory with direct interface to CPU. IEEE J. Solid State Circuits 31(4): 537-545 (1996) - 1991
- [j1]Jaime Jungok Bae, Tatsuya Suda, Naoya Watanabe:
Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes. IEEE J. Sel. Areas Commun. 9(9): 1496-1509 (1991)
1980 – 1989
- 1988
- [c3]Tatsuya Suda, Naoya Watanabe:
Evaluation of error recovery schemes for a high-speed packet switched network: link-by-link versus edge-to-edge schemes. INFOCOM 1988: 722-731 - 1986
- [c2]Naoya Watanabe, Ken-ichi Yukimatsu, Toshiaki Doi, Masachika Ishizura, Etsugo Yoneda, Makoto Kawashima, Kazuhiro Hayashi:
Network Testing for Digital Data Networks. ICC 1986: 588-592 - [c1]Ken-ichi Yukimatsu, Naoya Watanabe, Takashi Honda:
Multicast Communication Facilities in a High Speed Packet Switching Network. ICCC 1986: 276-281
Coauthor Index
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