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Kohji Takano
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2010 – 2019
- 2015
- [c11]Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama:
Single-channel full-duplex mmWave link using phased-array for Ethernet. CCNC 2015: 400-405 - 2014
- [c10]Daiju Nakano, Yasuteru Kohda, Kohji Takano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama:
60-GHz single-carrier coherent detection system with robust 16-QAM signal recovery. WCNC 2014: 341-346 - 2012
- [c9]Nobuyuki Ohba, Kohji Takano, Yasuteru Kohda, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama:
Multimedia content-downloading system using millimeter-wave attached memory. CCNC 2012: 94-98 - [c8]Yasunao Katayama, Toshiyuki Yamane, Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba:
MIMO link design strategy for wireless data center applications. WCNC 2012: 3302-3306 - 2011
- [c7]Daiju Nakano, Yasuteru Kohda, Kohji Takano, Toshiyuki Yamane, Nobuyuki Ohba, Yasunao Katayama:
Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique. COOL Chips 2011: 1-3 - [c6]Yasuteru Kohda, Nobuyuki Ohba, Kohji Takano, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama:
Instant multimedia contents downloading system using a 60-GHZ-2.4-GHZ hybrid wireless link. ICME 2011: 1-6 - [c5]Yasunao Katayama, Kohji Takano, Yasuteru Kohda, Nobuyuki Ohba, Daiju Nakano:
Wireless data center networking with steered-beam mmWave links. WCNC 2011: 2179-2184
2000 – 2009
- 2006
- [j2]Nobuyuki Ohba, Kohji Takano:
Hardware Design Verification Using Signal Transitions and Transactions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 1012-1017 (2006) - [c4]Nobuyuki Ohba, Kohji Takano:
Hardware debugging method based on signal transitions and transactions. ASP-DAC 2006: 454-459 - 2004
- [c3]Nobuyuki Ohba, Kohji Takano:
An SoC design methodology using FPGAs and embedded microprocessors. DAC 2004: 747-752 - 2003
- [j1]Akashi Satoh, Kohji Takano:
A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers 52(4): 449-460 (2003) - 2001
- [c2]Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
:
A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254 - 2000
- [c1]Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon:
High-Speed MARS Hardware. AES Candidate Conference 2000: 305-316
Coauthor Index
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