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Masaaki Kondo
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2020 – today
- 2024
- [j26]Yuri Alexeev, Maximilian Amsler, Marco Antonio Barroca, Sanzio Bassini, Torey Battelle, Daan Camps, David Casanova, Young Jay Choi, Frederic T. Chong, Charles Chung, Christopher Codella, Antonio D. Córcoles, James Cruise, Alberto Di Meglio, Ivan Duran, Thomas Eckl, Sophia E. Economou, Stephan J. Eidenbenz, Bruce Elmegreen, Clyde Fare, Ismael Faro, Cristina Sanz Fernández, Rodrigo Neumann Barros Ferreira
, Keisuke Fuji, Bryce Fuller, Laura Gagliardi, Giulia Galli, Jennifer R. Glick, Isacco Gobbi, Pranav Gokhale, Salvador de la Puente Gonzalez, Johannes Greiner, Bill Gropp, Michele Grossi, Emanuel Gull, Burns Healy, Matthew R. Hermes
Quantum-centric supercomputing for materials science: A perspective on challenges and future directions. Future Gener. Comput. Syst. 160: 666-710 (2024) - [c77]Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo:
DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference. DATE 2024: 1-6 - [i10]Yikai Mao, Shaswot Shresthamali, Masaaki Kondo:
Q-gen: A Parameterized Quantum Circuit Generator. CoRR abs/2407.18697 (2024) - [i9]Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu:
Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices. CoRR abs/2410.21073 (2024) - 2023
- [j25]Yuetsu Kodama, Masaaki Kondo, Mitsuhisa Sato:
Evaluation of Performance and Power Consumption on Supercomputer Fugaku Using SPEC HPC Benchmarks. IEICE Trans. Electron. 106(6): 303-311 (2023) - [j24]Jun Zhou, Masaaki Kondo:
An Interactive and Reductive Graph Processing Library for Edge Computing in Smart Society. IEICE Trans. Inf. Syst. 106(3): 319-327 (2023) - [j23]Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He
Adaptive Lossy Data Compression Extended Architecture for Memory Bandwidth Conservation in SpMV. IEICE Trans. Inf. Syst. 106(12): 2015-2025 (2023) - [j22]Siyi Hu
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications. Microprocess. Microsystems 102: 104895 (2023) - [j21]Takuya Kojima
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43(1): 49-57 (2023) - [j20]Kazuki Sunaga
Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. IEEE Micro 43(6): 66-73 (2023) - [j19]Jun Zhou
An Edge-Cloud Collaboration Framework for Graph Processing in Smart Society. IEEE Trans. Emerg. Top. Comput. 11(4): 985-1001 (2023) - [c76]Junyuan Zheng
Exploiting Data Parallelism in Graph-Based Simultaneous Localization and Mapping: A Case Study with GPU Accelerations. HPC Asia 2023: 126-139 - [c75]Junfeng Wu, Yuan He, Masaaki Kondo:
Accelerating Graph-Based SLAM through Data Parallelism and Mixed Precision on FPGAs. MCSoC 2023: 284-292 - [c74]Shaswot Shresthamali, Masaaki Kondo:
Enhancing Deep Reinforcement Learning with Compressed Sensing-based State Estimation. MCSoC 2023: 371-378 - [i8]Yikai Mao, Shaswot Shresthamali, Masaaki Kondo:
Quantum Circuit Fidelity Improvement with Long Short-Term Memory Networks. CoRR abs/2303.17523 (2023) - [i7]Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo:
DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference. CoRR abs/2305.07376 (2023) - 2022
- [j18]Jinyu Jiao, Yuan He
Enabling circuit-switching in modern on-chip networks. Microprocess. Microsystems 95: 104712 (2022) - [c73]Takuya Kojima
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS 2022: 1-3 - [c72]Ryuichi Sakamoto, Yuriko Ezaki, Masaaki Kondo:
Hash Distributed A* on an FPGA. HEART 2022: 76-83 - [c71]Yosuke Ueno
QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. HPCA 2022: 274-287 - [c70]Jun Zhou, Masaaki Kondo:
Interactive and Reliable Graph Processing via the Edge-Cloud Collaboration Framework. HPCC/DSS/SmartCity/DependSys 2022: 388-395 - [c69]Man Wu
ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. HPCC/DSS/SmartCity/DependSys 2022: 546-553 - [c68]Shaswot Shresthamali, Yuan He
FAWS: Fault-Aware Weight Scheduler for DNN Computations in Heterogeneous and Faulty Hardware. ISPA/BDCloud/SocialCom/SustainCom 2022: 204-212 - [c67]Siyi Hu, Makiko Ito, Takahide Yoshikawa, Yuan He
Memory Bandwidth Conservation for SpMV Kernels Through Adaptive Lossy Data Compression. PDCAT 2022: 467-480 - [c66]Siyi Hu, Masaaki Kondo, Yuan He
GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications. PDP 2022: 135-143 - [i6]Hiroki Matsutani, Mineto Tsukada, Masaaki Kondo:
On-Device Learning: A Neural Network Based Field-Trainable Edge AI. CoRR abs/2203.01077 (2022) - [i5]Yosuke Ueno
NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. CoRR abs/2208.05758 (2022) - 2021
- [j17]Yuan He
Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems. IEICE Trans. Electron. 104-C(6): 237-246 (2021) - [c65]Yuetsu Kodama, Masaaki Kondo, Mitsuhisa Sato:
Evaluation of SPEC CPU and SPEC OMP on the A64FX. CLUSTER 2021: 553-561 - [c64]Yosuke Ueno
QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. DAC 2021: 451-456 - [c63]Jun Zhou, Masaaki Kondo:
A Lightweight Interactive Graph Processing Library for Edge Computing in Smart Society. CANDAR (Workshops) 2021: 62-68 - [c62]Yunjiao Ma, Yuan He
Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL. CANDAR (Workshops) 2021: 94-100 - [c61]Motoki Sakurai, Yosuke Ueno
Path Planning and Moving Obstacle Avoidance with Neuromorphic Computing. ISR 2021: 209-215 - [c60]Shaswot Shresthamali, Masaaki Kondo, Hiroshi Nakamura
Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes. MCSoC 2021: 98-105 - [c59]Yuan He
Local Traffic-Based Energy-Efficient Hybrid Switching for On-Chip Networks. PDP 2021: 198-206 - [c58]Hiroki Oikawa, Masaaki Kondo:
Density-Based Data Selection and Management for Edge Computing. PerCom 2021: 1-11 - [c57]Yang Qin, Masaaki Kondo:
MLMG: Multi-Local and Multi-Global Model Aggregation for Federated Learning. PerCom Workshops 2021: 565-571 - [i4]Michael Gerndt, Masaaki Kondo, Barton P. Miller, Tapasya Patki:
Adaptive Resource Management for HPC Systems (Dagstuhl Seminar 21441). Dagstuhl Reports 11(10): 1-19 (2021) - 2020
- [j16]Mineto Tsukada
A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. IEEE Trans. Computers 69(7): 1027-1044 (2020) - [c56]Yuan He
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching. ACM Great Lakes Symposium on VLSI 2020: 241-246 - [c55]Ryuichi Sakamoto, Masaaki Kondo, Kohei Fujita, Tsuyoshi Ichimura, Kengo Nakajima:
The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption. HPC Asia 2020: 199-206 - [c54]Yang Qin, Hiroki Matsutani, Masaaki Kondo:
A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. iThings/GreenCom/CPSCom/SmartData/Cybermatics 2020: 684-691 - [c53]Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo:
Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. ITSC 2020: 1-8 - [i3]Yuan He, Jinyu Jiao, Thang Cao, Masaaki Kondo:
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching. CoRR abs/2005.08478 (2020)
2010 – 2019
- 2019
- [c52]Rei Ito, Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
An Adaptive Abnormal Behavior Detection using Online Sequential Learning. CSE/EUC 2019: 436-440 - [c51]Shaswot Shresthamali
Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning. ICCD 2019: 638-647 - [c50]Sayaka Terashima, Takuya Kojima
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - [i2]Kentaro Fukamizu, Masaaki Kondo, Ryuichi Sakamoto:
Generation High resolution 3D model from natural language by Generative Adversarial Network. CoRR abs/1901.07165 (2019) - [i1]Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
A Neural Network Based On-device Learning Anomaly Detector for Edge Devices. CoRR abs/1907.10147 (2019) - 2018
- [j15]Nobutaka Doba, Hiroyuki Fukuda, Kazushi Numata, Yoshiteru Hao, Kouji Hara, Akito Nozaki
A new device for fiducial registration of image-guided navigation system for liver RFA. Int. J. Comput. Assist. Radiol. Surg. 13(1): 115-124 (2018) - [c49]Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. Euro-Par Workshops 2018: 518-529 - [c48]Ryuichi Sakamoto, Tapasya Patki, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Daniel A. Ellsworth, Barry Rountree, Martin Schulz
Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers. IPDPS 2018: 526-535 - [c47]Yasutaka Wada
A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems. SCFA 2018: 199-218 - 2017
- [j14]Shaswot Shresthamali
Adaptive Power Management in Solar Energy Harvesting Sensor Node Using Reinforcement Learning. ACM Trans. Embed. Comput. Syst. 16(5s): 181:1-181:21 (2017) - [c46]Thang Cao, Wei Huang, Yuan He
Cooling-Aware Job Scheduling and Node Allocation for Overprovisioned HPC Systems. IPDPS 2017: 728-737 - [c45]Ryuichi Sakamoto, Thang Cao, Masaaki Kondo, Koji Inoue, Masatsugu Ueda, Tapasya Patki, Daniel A. Ellsworth, Barry Rountree, Martin Schulz
Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework. IPDPS 2017: 957-966 - [c44]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c43]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura
Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC 2017: 155-156 - [c42]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC 2017: 13-20 - 2016
- [j13]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - [j12]Yuan He
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. 99-D(12): 2881-2890 (2016) - [c41]Cao Thang, Yuan He
Demand-Aware Power Management for Power-Constrained HPC Systems. CCGrid 2016: 21-31 - [c40]Yuan He
Opportunistic circuit-switching for energy efficient on-chip networks. VLSI-SoC 2016: 1-6 - 2015
- [j11]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - [c39]Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue:
A flexible hardware barrier mechanism for many-core processors. ASP-DAC 2015: 61-68 - [c38]Yuan He
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD 2015: 455-458 - [c37]Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz
Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. SC 2015: 78:1-78:12 - 2014
- [c36]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c35]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c34]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - 2013
- [j10]Hiroshi Nakamura
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j9]Son-Truong Nguyen, Masaaki Kondo, Tomoya Hirao, Koji Inoue:
A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards. IEICE Trans. Inf. Syst. 96-D(8): 1645-1653 (2013) - [j8]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c33]Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue:
SMYLEref: A reference architecture for manycore-processor SoCs. ASP-DAC 2013: 561-564 - [c32]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c31]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c30]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - 2012
- [c29]Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga:
FLAT: a GPU programming framework to provide embedded MPI. GPGPU@ASPLOS 2012: 20-29 - [c28]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c27]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j7]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j6]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j5]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [c26]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c25]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c24]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - 2010
- [c23]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c22]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37
2000 – 2009
- 2009
- [j4]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 848-852 (2009) - [c21]Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura
Power-performance modeling of heterogeneous cluster-based web servers. GRID 2009: 225-231 - [c20]Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Cooperative shared resource access control for low-power chip multiprocessors. ISLPED 2009: 177-182 - [c19]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [c18]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 - 2007
- [j3]Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura:
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. SIGARCH Comput. Archit. News 35(1): 31-38 (2007) - [c17]Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
An intra-task dvfs technique based on statistical analysis of hardware events. Conf. Computing Frontiers 2007: 123-130 - [c16]Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE 2007: 797-802 - [c15]Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura
Power reduction of chip multi-processors using shared resource control cooperating with DVFS. ICCD 2007: 615-622 - [c14]Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura
A High Performance Cluster System Design by Adaptie Power Control. IPDPS 2007: 1-8 - 2006
- [j2]Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3519-3528 (2006) - [c13]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Energy-efficient dynamic instruction scheduling logic through instruction grouping. ISLPED 2006: 43-48 - 2005
- [c12]Masaaki Kondo, Hiroshi Nakamura
A Small, Fast and Low-Power Register File by Bit-Partitioning. HPCA 2005: 40-49 - [c11]Chikafumi Takahashi, Mitsuhisa Sato, Daisuke Takahashi
Empirical Study for Optimization of Power-Performance with On-Chip Memory. ISHPC 2005: 466-479 - [c10]Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
Dynamic Instruction Cascading on GALS Microprocessors. PATMOS 2005: 30-39 - 2004
- [c9]Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
Data Movement Optimization for Software-Controlled On-Chip Memory. Interaction between Compilers and Computer Architectures 2004: 120-127 - [c8]Masaaki Kondo, Hiroshi Nakamura
Dynamic Processor Throttling for Power Efficient Computations. PACS 2004: 120-134 - [c7]Hiroshi Nakamura
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS 2004: 116-125 - [c6]Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi
SCIMA-SMP: on-chip memory processor architecture for SMP. WMPI 2004: 121-128 - 2002
- [j1]Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura:
Software-controlled on-chip memory for high-performance and low-power computing. SIGARCH Comput. Archit. News 30(3): 7-8 (2002) - [c5]T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) 2002: 211-216 - [c4]Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura
Cache Line Impact on 3D PDE Solvers. ISHPC 2002: 301-309 - 2000
- [c3]Kazuya Takeda, Masaaki Kondo, Fumitada Itakura:
An acoustic measure for predicting recognition performance degradation. ICASSP 2000: 1739-1742 - [c2]Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku:
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. ICCD 2000: 105-111 - [c1]Hiroshi Nakamura
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. Intelligent Memory Systems 2000: 15-32
Coauthor Index
[j23] [j22] [c66] [c60] [c51] [j14] [c44] [c43] [c42] [j13] [j12] [j11] [c38] [c36] [c35] [c34] [j10] [j8] [c32] [c31] [c30] [c28] [c27] [r1] [j7] [j6] [j5] [c26] [c25] [c24] [c23] [c22] [j4] [c21] [c20] [c19] [c18] [j3] [c17] [c16] [c15] [c14] [j2] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [j1] [c5] [c4] [c2] [c1]
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