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2020 – today
- 2024
- [j28]Yu-Ping Huang
, Yu-Sian Lu, Wei-Zen Chen:
A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction. IEEE Open J. Circuits Syst. 5: 291-301 (2024) - 2023
- [j27]Wei-Jhih Jian
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration. IEEE J. Solid State Circuits 58(4): 993-1001 (2023) - [j26]Yao-Chia Liu
A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement. IEEE J. Solid State Circuits 58(10): 2801-2811 (2023) - 2022
- [c36]Wei-Jhih Jian, Wei-Zen Chen:
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrms Resolution with Background Self-Calibration. VLSI Technology and Circuits 2022: 8-9 - 2021
- [j25]Robert Chen-Hao Chang
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 56(10): 2900-2901 (2021) - [j24]Wei-Hsiang Ho
A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology. IEEE Open J. Circuits Syst. 2: 56-64 (2021) - [j23]Yu-Ting Lin
A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2820-2824 (2021) - [c35]Yu-Ping Huang, Yi-Wei Chang, Wei-Zen Chen:
A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector. A-SSCC 2021: 1-2 - [c34]Yu-Sian Liao, Wei-Zen Chen:
A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration. A-SSCC 2021: 1-3 - [c33]Yu-Sian Lu, Cheng-Lung Lee, Wei-Zen Chen:
A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction. A-SSCC 2021: 1-2 - [c32]Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany:
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC 2021: 178-179 - [c31]Tony Chan Carusone, Sudip Shekhar, Yohan Frans, Wei-Zen Chen, Thomas Toifl, Munehiko Nagatani, Franz Dielacher, William Redman-White:
F6: Optical and Electrical Transceivers for 400GbE and Beyond. ISSCC 2021: 533-536 - 2020
- [j22]Abhishek Patyal
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5056-5068 (2020) - [c30]Yu-Ting Lin, Wei-Zen Chen:
A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. A-SSCC 2020: 1-2 - [c29]Wei-Hsiang Ho, Yi-Hsun Hsieh, Boris Murmann, Wei-Zen Chen:
A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology. ISCAS 2020: 1-4 - [c28]Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen:
A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [j21]Yuan-Sheng Lee
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery. IEEE J. Solid State Circuits 54(8): 2243-2254 (2019) - 2018
- [c27]Chia-Tse Hung, Yu-Ping Huang, Wei-Zen Chen:
A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. A-SSCC 2018: 213-214 - [c26]Yuan-Sheng Lee, Wei-Zen Chen:
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery. ISCAS 2018: 1-4 - 2017
- [j20]Shih-Hao Huang
A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS. IEEE J. Solid State Circuits 52(3): 747-756 (2017) - 2016
- [j19]Zhiyuan Ren, Hsiao-Hwa Chen, Wei-Zen Chen:
Distortion-characteristic estimation predistorter for high efficiency power amplifiers. IET Signal Process. 10(9): 1024-1030 (2016) - [c25]Wei-Zen Chen, Po-I Kuo:
A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement. ESSCIRC 2016: 347-350 - 2015
- [j18]Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen:
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. IEEE J. Solid State Circuits 50(11): 2625-2634 (2015) - [j17]Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 743-751 (2015) - [j16]Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen:
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 766-770 (2015) - [c24]Hung-Kai Chen, Wei-Zen Chen, Zhiyuan Ren
A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter. ASICON 2015: 1-4 - [c23]Shih-Hao Huang, Wei-Zen Chen:
A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver. VLSIC 2015: 120- - 2014
- [j15]Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Kai-Ting Chang:
A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1648-1655 (2014) - [c22]Wei-Zen Chen, Yi-Hung Yang:
An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer. APCCAS 2014: 659-662 - [c21]Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen:
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. A-SSCC 2014: 97-100 - [c20]Zheng-Hao Hong, Wei-Zen Chen:
A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. A-SSCC 2014: 277-280 - [c19]Jhong-Ting Jian, Yu-Lin Song
A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer. ISCAS 2014: 874-877 - [c18]Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan
An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. VLSI-DAT 2014: 1-4 - 2013
- [j14]Tai-You Lu, Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu:
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 257-267 (2013) - [c17]Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan:
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. CICC 2013: 1-4 - [c16]Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. CICC 2013: 1-4 - [c15]Chien-Hung Chen, Wei-Zen Chen:
A 10Bit, 10MS/s, low power cyclic ADC. ICICDT 2013: 155-158 - 2012
- [j13]Wei-Zen Chen, Tai-You Lu, Wei-Wen Ou, Shun-Tien Chou, Song-Yu Yang:
A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(3): 505-514 (2012) - [j12]Tai-You Lu, Wei-Zen Chen:
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 948-958 (2012) - [c14]Shun-Tien Chou, Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen:
A 40 Gbps optical receiver analog front-end in 65 nm CMOS. ISCAS 2012: 1736-1739 - [c13]Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao:
A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. VLSIC 2012: 12-13 - 2011
- [j11]Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang, Yang-Tung Huang:
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology. IEEE J. Solid State Circuits 46(5): 1158-1169 (2011) - [c12]Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan
Fast analog layout prototyping for nanometer design migration. ICCAD 2011: 517-522 - 2010
- [j10]Song-Yu Yang, Wei-Zen Chen, Tai-You Lu:
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. IEEE J. Solid State Circuits 45(3): 578-586 (2010) - [c11]Wei-Zen Chen, Wei-Wen Ou, Tai-You Lu, Shun-Tien Chou, Song-Yu Yang:
A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation. ISCAS 2010: 1627-1630
2000 – 2009
- 2009
- [j9]Wei-Zen Chen, Ruei-Ming Gan, Shih-Hao Huang:
A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(10): 2325-2331 (2009) - [c10]Shih-Hao Huang, Wei-Zen Chen:
A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector. CICC 2009: 129-132 - [c9]Song-Yu Yang, Wei-Zen Chen:
A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. ISSCC 2009: 90-91 - 2008
- [j8]Wei-Zen Chen, Guan-Sheng Huang:
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(6): 1495-1501 (2008) - [c8]Tai-You Lu, Wei-Zen Chen:
A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System. ISSCC 2008: 126-127 - 2007
- [j7]Wei-Zen Chen, Wen-Hui Chen, Kuo-Ching Hsu:
Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(7): 1413-1423 (2007) - [j6]Wei-Zen Chen, Da-Shin Lin:
A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 358-365 (2007) - [c7]Wei-Zen Chen, Shih-Hao Huang:
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector. CICC 2007: 293-296 - 2006
- [j5]Wei-Zen Chen, Chao-Hsin Lu:
Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 977-983 (2006) - [c6]Wei-Zen Chen, Guan-Sheng Huang:
A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications. ISCAS 2006 - 2005
- [j4]Wei-Zen Chen, Ying-Lien Cheng, Da-Shin Lin:
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end. IEEE J. Solid State Circuits 40(6): 1388-1396 (2005) - [c5]Wei-Zen Chen, Kuo-Ching Hsu:
Miniaturized 3-dimensional transformer design. CICC 2005: 285-288 - 2004
- [j3]Wei-Zen Chen, Jia-Xian Chang, Ying-Jen Hong, Meng-Tzer Wong, Chien-Liang Kuo:
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process. IEEE J. Solid State Circuits 39(1): 234-237 (2004) - [c4]Wei-Zen Chen, Ying-Lien Cheng:
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end. ESSCIRC 2004: 263-266 - 2003
- [c3]Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu:
10 GHz quadrature-phase voltage controlled oscillator and prescaler. ESSCIRC 2003: 361-364 - 2002
- [c2]Wei-Zen Chen, Chao-Hsin Lu:
A 2.5 Gbps CMOS optical receiver analog front-end. CICC 2002: 359-362
1990 – 1999
- 1999
- [j2]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V, 1.8-GHz BJT phase-locked loop. IEEE J. Solid State Circuits 34(6): 784-789 (1999) - 1998
- [j1]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V 2-GHz BJT variable frequency oscillator. IEEE J. Solid State Circuits 33(9): 1406-1410 (1998) - [c1]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2 V 1.6 GHz BJT phase-locked loop. CICC 1998: 563-566
Coauthor Index
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