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Chung-Ping Chung
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2010 – 2019
- 2015
- [j41]I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors. J. Inf. Sci. Eng. 31(4): 1431-1453 (2015) - 2014
- [j40]Tsung-Hsi Weng, Chung-Ping Chung:
Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering. Future Gener. Comput. Syst. 37: 76-87 (2014) - [j39]I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Chung-Ping Chung:
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13(4): 92:1-92:28 (2014) - 2011
- [j38]I-Wei Wu, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration. J. Inf. Sci. Eng. 27(5): 1641-1657 (2011) - [j37]Yung-Cheng Ma, Chung-Ping Chung, Tien-Fu Chen:
Load and storage balanced posting file partitioning for parallel information retrieval. J. Syst. Softw. 84(5): 864-884 (2011) - [c33]Tsung-Hsi Weng, Yi-Ting Wang, Chung-Ping Chung:
Exploiting Parallelism in the H.264 Deblocking Filter by Operation Reordering. ICA3PP (1) 2011: 80-92 - [c32]Peter Deayton, Chung-Ping Chung:
Set Utilization Based Dynamic Shared Cache Partitioning. ICPADS 2011: 284-291 - [c31]Walter Yuan-Hwa Li, Chin-Ling Huang, Chung-Ping Chung:
Tolerating Load Miss-Latency by Extending Effective Instruction Window with Low Complexity. ICPP 2011: 83-92 - 2010
- [c30]Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP 2010: 115-118
2000 – 2009
- 2009
- [c29]Yi-Chi Chen, Hui-Chin Yang, Chung-Ping Chung, Wei-Ting Wang:
Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing. CSE (2) 2009: 31-36 - [c28]Chung-Ping Chung, Hong-Wei Chen, Hui-Chin Yang:
Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads. CSE (2) 2009: 402-407 - [c27]Chih-Chieh Hsiao, Chung-Ping Chung, Hui-Chin Yang:
A Hierarchical Primitive Lists Structure for Tile-Based Rendering. CSE (2) 2009: 408-413 - [c26]Hsiu-ching Hsieh, Chih-Chieh Hsiao, Hui-Chin Yang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Methods for Precise False-Overlap Detection in Tile-Based Rendering. CSE (2) 2009: 414-419 - [c25]Chung-Ping Chung, Tung-Lin Lu, Hui-Chin Yang:
H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method. CSE (2) 2009: 420-425 - [c24]Oluwayomi B. Adamo, Afrin Naz, Tommy Janjusic, Krishna M. Kavi, Chung-Ping Chung:
Smaller Split L-1 Data Caches for Multi-core Processing Systems. ISPAN 2009: 74-79 - 2008
- [j36]Wei-Hau Chiao, Chung-Ping Chung:
Filtering of Unnecessary Branch Predictor Lookups for Low-power Processor Architecture. J. Inf. Sci. Eng. 24(4): 1127-1142 (2008) - [c23]Shun-Chieh Chang, W. Y. Li, Yuan-Jung Kuo, Chung-Ping Chung:
Early load: Hiding load latency in deep pipeline processor. ACSAC 2008: 1-8 - [c22]Guan-Ying Chiu, Hui-Chin Yang, Walter Yuan-Hwa Li, Chung-Ping Chung:
Mechanism for return stack and branch history corrections under misprediction in deep pipeline design. ACSAC 2008: 1-8 - [c21]Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. DAC 2008: 776-779 - [c20]I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Instruction Set Extension Exploration in Multiple-Issue Architecture. DATE 2008: 764-769 - [c19]Hui-Chin Yang, Li-Ming Wang, Chung-Ping Chung:
iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability. ICYCS 2008: 1309-1313 - 2007
- [c18]Wei-Ting Wang, Yi-Chi Chen, Chung-Ping Chung:
A Run-Time Reconfigurable Fabric for 3D Texture Filtering. ASAP 2007: 180-185 - [c17]Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung:
Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing. ERSA 2007: 99-106 - [c16]I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints. HiPEAC 2007: 291-305 - 2006
- [j35]Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. Inf. Process. Manag. 42(2): 407-428 (2006) - [j34]Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. Inf. Process. Manag. 42(3): 729-750 (2006) - [c15]Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung:
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. CDES 2006: 91-96 - [c14]Hui-Chin Yang, Chung-Ping Chung:
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability. CDES 2006: 146-152 - 2005
- [j33]Wann-Yun Shieh, Chung-Ping Chung:
A statistics-based approach to incrementally update inverted files. Inf. Process. Manag. 41(2): 275-288 (2005) - [j32]Ching-Wen Chen, Chung-Ping Chung:
Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving. J. Supercomput. 34(1): 63-80 (2005) - [c13]Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu:
Low-Power Data Address Bus Encoding Method. CDES 2005: 204-210 - [c12]Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen:
Low-Power Branch Prediction. CDES 2005: 211-217 - 2004
- [j31]Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung:
Branch-and-bound task allocation with task clustering-based pruning. J. Parallel Distributed Comput. 64(11): 1223-1240 (2004) - [j30]Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Code compression by register operand dependency. J. Syst. Softw. 72(3): 295-304 (2004) - [j29]Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung:
A software/hardware cooperated stack operations folding model for Java processors. J. Syst. Softw. 72(3): 377-387 (2004) - [c11]Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung:
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. ITCC (2) 2004: 229-235 - 2003
- [j28]Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Inverted file compression through document identifier reassignment. Inf. Process. Manag. 39(1): 117-131 (2003) - [j27]Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung:
An Inverted File Cache for Fast Information Retrieval. J. Inf. Sci. Eng. 19(4): 681-695 (2003) - [j26]Ching-Wen Chen, Neng-Pin Lu, Chung-Ping Chung:
3-Disjoint gamma interconnection networks. J. Syst. Softw. 66(2): 129-134 (2003) - [j25]Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung:
Variable-size data item placement for load and storage balancing. J. Syst. Softw. 66(2): 157-166 (2003) - [j24]Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Compressing MIPS code by multiple operand dependencies. ACM Trans. Embed. Comput. Syst. 2(4): 482-508 (2003) - [c10]Wann-Yun Shieh, Chung-Ping Chung:
A Statistics-Based Approach to Incrementally Update Inverted Files. IKE 2003: 38-43 - [c9]Wann-Yun Shieh, Tien-Fu Chen, Chung-Ping Chung:
A Tree-Based inverted File for Fast Ranked-Document Retrieval. IKE 2003: 64-69 - 2002
- [j23]Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung:
Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. J. Inf. Sci. Eng. 18(3): 393-409 (2002) - [j22]Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung:
An analytical POC stack operations folding for continuous and discontinuous Java bytecodes. J. Syst. Archit. 48(1-3): 1-16 (2002) - [j21]Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung:
Posting file partitioning and parallel information retrieval. J. Syst. Softw. 63(2): 113-127 (2002) - [j20]Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Design of an optimal folding mechanism for Java processors. Microprocess. Microsystems 26(8): 341-352 (2002) - [c8]Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Code Compression by Register Operand Dependency. Interaction between Compilers and Computer Architectures 2002: 91-101 - 2001
- [j19]Ching-Wen Chen, Chung-Ping Chung:
Fault-tolerant gamma interconnection network without backtracking. J. Syst. Softw. 58(1): 23-31 (2001) - [j18]Yung-Cheng Ma, Chung-Ping Chung:
A dominance relation enhanced branch-and-bound task allocation. J. Syst. Softw. 58(2): 125-134 (2001) - 2000
- [j17]R.-Ming Shiu, Neng-Pin Lu, Chung-Ping Chung:
Applying stack simulation for branch target buffers. J. Syst. Softw. 52(1): 67-78 (2000) - [c7]Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung:
Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note). Euro-Par 2000: 994-997 - [c6]Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung:
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ICCD 2000: 294-299
1990 – 1999
- 1999
- [j16]Ruey-Liang Ma, Chung-Ping Chung:
Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System. J. Inf. Sci. Eng. 15(6): 859-884 (1999) - 1997
- [c5]Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ruey-Liang Ma, Dze-Chaung Wang, Chung-Ping Chung:
Instruction Folding in Java Processor. ICPADS 1997: 138-143 - [c4]Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung:
Instruction Cache Prefetching with Extended BTB. ICPADS 1997: 360- - 1996
- [j15]Neng-Pin Lu, Chung-Ping Chung:
A Fault-Tolerant Multistage Combining Network. J. Parallel Distributed Comput. 34(1): 14-28 (1996) - [c3]Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung:
Register renaming for x86 superscalar design. ICPADS 1996: 336-343 - 1995
- [j14]Ruey-Liang Ma, Chung-Ping Chung:
Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog. Comput. J. 38(6): 457-470 (1995) - [j13]Ren-Lianq Cheng, Chung-Ping Chung:
An Approximate Agreement Algorithm for Wraparound Meshes. Int. J. High Speed Comput. 7(3): 407-419 (1995) - [j12]Neng-Pin Lu, Chung-Ping Chung:
Memory System Design in Superscalar Processing. Int. J. High Speed Comput. 7(3): 421-443 (1995) - [j11]Hong Chich Chou, Chung-Ping Chung:
An Optimal Instruction Scheduler for Superscalar Processor. IEEE Trans. Parallel Distributed Syst. 6(3): 303-313 (1995) - 1994
- [j10]Hong Chich Chou, Chung-Ping Chung:
Optimal multiprocessor task scheduling using dominance and equivalence relations. Comput. Oper. Res. 21(4): 463-475 (1994) - [j9]Yuh-Horng Shiau, Chung-Ping Chung:
Effects and Handling of Instruction Class Contention in Superscalar Processing. Int. J. High Speed Comput. 6(3): 357-373 (1994) - [c2]Tang-Show Hwang, Chung-Ping Chung:
Delayed Precise Invalidation - A Software Cache Coherence Scheme. ICPADS 1994: 524-529 - [c1]Ruey-Liang Ma, Chung-Ping Chung:
Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog. ICPADS 1994: 744-751 - 1993
- [j8]Hong Chich Chou, Chung-Ping Chung:
Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm. BIT 33(3): 354-371 (1993) - [j7]Ren-Lianq Cheng, Chung-Ping Chung:
Reaching Approximate Agreement on Hypercube. Parallel Comput. 19(7): 765-775 (1993) - 1992
- [j6]Chung-Ping Chung, Wen-Yang Lin:
Vectorization of Sorting Algorithms. Int. J. High Speed Comput. 4(3): 213-232 (1992) - [j5]Hong Chich Chou, Chung-Ping Chung:
Upper Bound Analysis of Scheduling Arbitrary-Delay Instructions on Typed Pipelined Processors. Int. J. High Speed Comput. 4(4): 301-312 (1992) - [j4]Hong Chich Chou, Chung-Ping Chung:
A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle. Parallel Comput. 18(4): 393-399 (1992) - [j3]Yuh-Horng Shiau, Chung-Ping Chung:
Adoptability and effectiveness of microcode compaction algorithms in superscalar processing. Parallel Comput. 18(5): 497-510 (1992) - 1991
- [j2]Cheng Chen, Chung-Ping Chung, Cheng-Chin Chiang, Hsin-Chia Fu, S. J. Wang:
An Or-Parallel Inference Model Based on Multi RISC-Style Processing System. J. Inf. Sci. Eng. 7(4): 487-512 (1991)
1980 – 1989
- 1989
- [j1]Chung-Ping Chung, Shyi-Chyi Jeng, Hong Chich Chou, Cheng Chen:
Design of Dual-ALU CRISC and Its Concurrent Execution . J. Inf. Sci. Eng. 5(3): 251-274 (1989)
Coauthor Index
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