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Jiann-Chyi Rau
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2020 – today
- 2024
- [c24]Jiann-Chyi Rau, Wei-Bin Yang, Yu-Lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang:
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. ISOCC 2024: 262-263 - 2021
- [c23]Jiann-Chyi Rau, Jia-Xiang Wang:
A Scan-Based Lower-Power Testing Architecture for Modern Circuits. ISPACS 2021: 1-2
2010 – 2019
- 2013
- [j3]Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau:
Compact Test Pattern Selection for Small Delay Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 971-975 (2013) - 2012
- [c22]Ding-ke Weng, Jiann-Chyi Rau, Cheng-Han Lin:
Optimal unknown bit filtering for test response masking. ISPACS 2012: 787-791 - 2011
- [j2]Jiann-Chyi Rau, Po-Han Wu:
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment. IET Comput. Digit. Tech. 5(1): 25-35 (2011) - 2010
- [c21]Gong-Han Chen, Chu-Chuan Lin, Po-Han Wu, Jiann-Chyi Rau:
Multi-cycle compress technique for high-speed IP in low-cost environment. ISCAS 2010: 437-440 - [c20]Gong-Han Chen, Po-Han Wu, Jiann-Chyi Rau:
Multi-chains encoding scheme in low-cost ATE. ISCAS 2010: 1587-1590 - [c19]Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng:
The AB-filling methodology for power-aware at-speed scan testing. ITC 2010: 807
2000 – 2009
- 2009
- [c18]Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau:
New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology. Asian Test Symposium 2009: 105-110 - [c17]Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau:
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression. ISCAS 2009: 2986-2989 - [c16]Po-Han Wu, Jiann-Chyi Rau:
Low power multi-chains encoding scheme for SoC in low-cost environment. ITC 2009: 1 - 2008
- [c15]Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li, Jiann-Chyi Rau:
An efficient test-data compaction for low power VLSI testing. EIT 2008: 237-241 - [c14]Wei-Lin Li, Tsung-Tang Chen, Po-Han Wu, Jiann-Chyi Rau:
Test slice difference technique for low power encoding. HLDVT 2008: 25-32 - [c13]Chia-Jung Liu, Yi-Chen Lin, Jiann-Chyi Rau:
The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design. ICECS 2008: 462-465 - 2006
- [c12]Jiann-Chyi Rau, Chien-Shiun Chen, Po-Han Wu:
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs. APCCAS 2006: 1399-1402 - [c11]Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu:
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. APCCAS 2006: 1883-1886 - [c10]Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen:
A broadcast-based test scheme for reducing test size and application time. ISCAS 2006 - 2005
- [c9]Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu:
A novel reseeding mechanism for pseudo-random testing of VLSI circuits. ISCAS (3) 2005: 2979-2982 - [c8]Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma:
Reconfigurable multiple scan-chains for reducing test application time of SOCs. ISCAS (6) 2005: 5846-5849 - 2004
- [c7]Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang:
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains. Asian Test Symposium 2004: 82-87 - 2003
- [c6]Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin:
An Efficient Mechanism for Debugging RTL Description. IWSOC 2003: 370-373 - [c5]Jiann-Chyi Rau, Kuo-Chun Kuo:
An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits. IWSOC 2003: 374-377 - 2002
- [c4]Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang:
A don't-care based image circuit for function verification. ISCAS (5) 2002: 325-328 - 2001
- [j1]Shih-Chieh Chang, Jiann-Chyi Rau:
A timing-driven pseudoexhaustive testing for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 147-158 (2001) - 2000
- [c3]Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang:
A compact factored form for a Boolean function. ISCAS 2000: 317-320 - [c2]Shih-Chieh Chang, Jiann-Chyi Rau:
A timing-driven pseudo-exhaustive testing of VLSI circuits. ISCAS 2000: 665-668
1990 – 1999
- 1998
- [c1]Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC 1998: 322-330
Coauthor Index
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