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Lei Jin 0002
Person information
- affiliation: University of Pittsburgh, Department of Computer Science, PA, USA
- affiliation (former): Zhejiang University, China
- not to be confused with: Lei Jin 0003
Other persons with the same name
- Lei Jin — disambiguation page
- Lei Jin 0001 — Arkansas University, Department of Computer Science, Little Rock, AR, USA
- Lei Jin 0003
— University of Pittsburgh, School of Information Sciences, PA, USA (and 1 more)
- Lei Jin 0004
- Lei Jin 0005
- Lei Jin 0006
- Lei Jin 0007 — Xiamen University of Technology, College of Environmental Science and Engineering, Xiamen, China (and 1 more)
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2010 – 2019
- 2011
- [j2]Lei Jin, Sangyeun Cho:
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse. IEEE Trans. Computers 60(4): 526-537 (2011) - 2010
- [j1]Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho:
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. Softw. Pract. Exp. 40(3): 239-258 (2010)
2000 – 2009
- 2009
- [c7]Lei Jin, Sangyeun Cho:
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. PACT 2009: 361-371 - 2008
- [c6]Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng:
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. ICPP 2008: 446-453 - [c5]Lei Jin, Sangyeun Cho:
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches. ICPP 2008: 487-494 - 2007
- [c4]Sangyeun Cho, Lei Jin, Kiyeon Lee:
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. RTCSA 2007: 3-11 - 2006
- [c3]Lei Jin, Hyunjin Lee, Sangyeun Cho:
A flexible data to L2 cache mapping approach for future multicore processors. Memory System Performance and Correctness 2006: 92-101 - [c2]Lei Jin, Sangyeun Cho:
Reducing cache traffic and energy with macro data load. ISLPED 2006: 147-150 - [c1]Sangyeun Cho, Lei Jin:
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. MICRO 2006: 455-468
Coauthor Index
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