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Ilya Issenin
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2000 – 2009
- 2009
- [j6]Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Sanghyun Park, Yunheung Paek:
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 461-465 (2009) - [j5]Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek:
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 554-567 (2009) - [j4]Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian:
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1343-1347 (2009) - 2008
- [j3]Ilya Issenin, Nikil D. Dutt:
Using FORAY Models to Enable MPSoC Memory Optimizations. Int. J. Parallel Program. 36(1): 93-113 (2008) - [j2]Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt:
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1439-1452 (2008) - [c11]Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt:
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. ASP-DAC 2008: 328-333 - [c10]Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Yunheung Paek, SunJun Ko:
Compiler driven data layout optimization for regular/irregular array access patterns. LCTES 2008: 41-50 - 2007
- [j1]Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil D. Dutt:
DRDU: A data reuse analysis technique for efficient scratch-pad memory management. ACM Trans. Design Autom. Electr. Syst. 12(2): 15 (2007) - [c9]Doosan Cho, Ilya Issenin, Nikil D. Dutt, Jonghee W. Yoon, Yunheung Paek:
Software controlled memory layout reorganization for irregular array access patterns. CASES 2007: 179-188 - [c8]Ilya Issenin, Nikil D. Dutt:
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. IESS 2007: 299-312 - [i1]Ilya Issenin, Nikil D. Dutt:
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. CoRR abs/0710.4640 (2007) - 2006
- [c7]Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian:
Mitigating soft error failures for multimedia applications by selective data protection. CASES 2006: 411-420 - [c6]Ilya Issenin, Nikil D. Dutt:
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. CODES+ISSS 2006: 294-299 - [c5]Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt:
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. DAC 2006: 49-52 - 2005
- [c4]Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt:
Compilation techniques for energy reduction in horizontally partitioned cache architectures. CASES 2005: 90-96 - [c3]Ilya Issenin, Nikil D. Dutt:
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. DATE 2005: 808-813 - 2004
- [c2]Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil D. Dutt:
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. DATE 2004: 202-207 - 2002
- [c1]Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau:
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE 2002: 168-175
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