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Kai Ming Mok
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2020 – today
- 2023
- [j6]Zheng-Yan Wong, Denis Chee-Keong Wong
, Wai-Kong Lee
KaratSaber: New Speed Records for Saber Polynomial Multiplication Using Efficient Karatsuba FPGA Architecture. IEEE Trans. Computers 72(7): 1830-1842 (2023) - [j5]Jin-Chuan See, Hui-Fuang Ng
Cryptensor: A Resource-Shared Co-Processor to Accelerate Convolutional Neural Network and Polynomial Convolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4735-4748 (2023) - 2022
- [j4]Beng-Liong Tan, Kai Ming Mok
RISC32-LP: Low-Power FPGA-Based IoT Sensor Nodes With Energy Reduction Program Analyzer. IEEE Internet Things J. 9(6): 4214-4228 (2022) - 2021
- [j3]Zheng-Yan Wong
High-Speed RLWE-Oriented Polynomial Multiplier Utilizing Karatsuba Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 2157-2161 (2021) - 2020
- [j2]Jin-Chuan See
RISC32-E: Field programmable gate array based sensor node with queue system to support fast encryption in Industrial Internet of Things applications. Int. J. Circuit Theory Appl. 48(8): 1209-1226 (2020) - [j1]Wei Pau Kiat, Kai Ming Mok, Wai-Kong Lee
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications. Microprocess. Microsystems 73: 102966 (2020)
2010 – 2019
- 2017
- [c3]Wei Pau Kiat, Kai Ming Mok
A Comprehensive Analysis on Data Hazard for RISC32 5-Stage Pipeline Processor. AINA Workshops 2017: 154-159
2000 – 2009
- 2009
- [c2]Richard Yew Fatt Ng, Yong Haur Tay
DSP-Based Implementation and Optimization of an Iris Verification Algorithm Using Textural Feature. FSKD (5) 2009: 374-378 - [c1]Richard Yew Fatt Ng, Yong Haur Tay
Iris Verification Algorithm Based on Texture Analysis and its Implementation on DSP. ICSAP 2009: 198-202
Coauthor Index
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