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Chiou-Yng Lee
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2020 – today
- 2022
- [j59]Chiou-Yng Lee
, Medien Zeghid
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor. IEEE Access 10: 7926-7936 (2022) - [c41]Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie:
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. ISCAS 2022: 1160-1164 - 2021
- [c40]Jiafeng Xie, Pengzhou He, Chiou-Yng Lee:
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. ICCD 2021: 130-137 - 2020
- [c39]Chiou-Yng Lee, Jiafeng Xie:
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation. ASP-DAC 2020: 253-258
2010 – 2019
- 2019
- [j58]Chiou-Yng Lee
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 203-214 (2019) - [j57]Jeng-Shyang Pan
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1614-1622 (2019) - [j56]Jiafeng Xie
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2119-2130 (2019) - [c38]Jiafeng Xie, Chiou-Yng Lee:
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. FPGA 2019: 187 - [c37]Jiafeng Xie, Chiou-Yng Lee:
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field. ACM Great Lakes Symposium on VLSI 2019: 343-346 - [c36]Chiou-Yng Lee, Jiafeng Xie:
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB. HOST 2019: 21-30 - [c35]Chiou-Yng Lee, Jiafeng Xie:
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. ICCD 2019: 29-37 - [c34]Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher:
Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. ISCAS 2019: 1-5 - 2018
- [j55]Chiou-Yng Lee
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field. IEEE Access 6: 38234-38242 (2018) - [j54]Che Wun Chiou, Cheng-Min Lee, Yuh-Sien Sun, Chiou-Yng Lee, Jim-Min Lin:
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems. IET Comput. Digit. Tech. 12(5): 187-191 (2018) - [j53]Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m). IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2455-2465 (2018) - [j52]Jiafeng Xie
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. IEEE Trans. Multi Scale Comput. Syst. 4(4): 773-783 (2018) - [c33]Chiou-Yng Lee, Jiafeng Xie:
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. ICCD 2018: 187-194 - 2017
- [j51]Che Wun Chiou, Yuh-Sien Sun, Cheng-Min Lee, Jim-Min Lin, Tai-Pao Chuang, Chiou-Yng Lee:
Gaussian normal basis multiplier over GF(2 m ) using hybrid subquadratic-and-quadratic TMVP approach for elliptic curve cryptography. IET Circuits Devices Syst. 11(6): 579-588 (2017) - [j50]Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh, Jeng-Shyang Pan
Low-latency digit-serial dual basis multiplier for lightweight cryptosystems. IET Inf. Secur. 11(6): 301-311 (2017) - [j49]Chiou-Yng Lee
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 735-746 (2017) - [c32]Shu-Xia Dong, Jeng-Shyang Pan
Hardware implementation of double basis multiplier using TMVP approach over GF (2m). iCAST 2017: 486-493 - [c31]Pengfei Song, Jeng-Shyang Pan
An efficient FPGA-based accelerator design for convolution. iCAST 2017: 494-500 - 2016
- [j48]Chiou-Yng Lee
Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1316-1319 (2016) - [j47]Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu:
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2413-2425 (2016) - 2015
- [j46]Jeng-Shyang Pan
Subquadratic space complexity Gaussian normal basis multipliers over GF(2m) based on Dickson-Karatsuba decomposition. IET Circuits Devices Syst. 9(5): 336-342 (2015) - [j45]Ping-Hsu Chen, Yung-Hui Li, Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin:
A smart safety cane for human fall detection. Int. J. Ad Hoc Ubiquitous Comput. 20(1): 49-65 (2015) - [j44]Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 854-862 (2015) - [j43]Chiou-Yng Lee, Pramod Kumar Meher:
Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1091-1098 (2015) - [j42]Chung-Hsin Liu, Chiou-Yng Lee, Pramod Kumar Meher:
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2044-2051 (2015) - [j41]Chiou-Yng Lee, Pramod Kumar Meher:
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2846-2855 (2015) - [j40]Reza Azarderakhsh, Mehran Mozaffari Kermani
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1969-1972 (2015) - [c30]Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin:
Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination. ICGEC (2) 2015: 187-200 - [c29]Che Wun Chiou, Yuh-Sien Sun, Cheng-Min Lee, Y.-L. Chiu, Jim-Min Lin, Chiou-Yng Lee:
Problems on Gaussian Normal Basis Multiplication for Elliptic Curve Cryptosystem. ICGEC (2) 2015: 201-207 - [c28]Shyan-Ming Yuan
Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm. ICGEC (2) 2015: 221-231 - [c27]Wen-Yo Lee, Bo-Jhih Chen, Chieh-Tsai Wu
Implementation of an FPGA-Based Vision Localization. ICGEC (2) 2015: 233-242 - [c26]Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee, Jing-Rui Hsiao:
Supporting Physical Agents in an Interactive e-book. ICGEC (2) 2015: 243-252 - [c25]Jeng-Shyang Pan
Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). ISCAS 2015: 1430-1433 - 2014
- [j39]Jeng-Shyang Pan
Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach. IEEE Trans. Computers 63(5): 1169-1181 (2014) - [j38]Hong-Chun Hsu, Kuang-Shyr Wu, Cheng-Kuan Lin, Chiou-Yng Lee, Chien-Ping Chang:
A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model. IEEE Trans. Computers 63(12): 2894-2904 (2014) - [j37]Siavash Bayat Sarmadi, Mehran Mozaffari Kermani
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures. IEEE Trans. Circuits Syst. II Express Briefs 61-II(2): 125-129 (2014) - [j36]Chiou-Yng Lee, Chun-Sheng Yang, Bimal Kumar Meher, Pramod Kumar Meher, Jeng-Shyang Pan
Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3115-3124 (2014) - [j35]Chiou-Yng Lee, Pramod Kumar Meher, Chien-Ping Chang:
Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3125-3134 (2014) - [j34]Mehran Mozaffari Kermani
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 22(5): 995-1003 (2014) - [c24]Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee:
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. ISIC 2014: 176-179 - 2013
- [j33]Ying Yan Hua, Jim-Min Lin, Che Wun Chiou, Chiou-Yng Lee
Low space-complexity digit-serial dual basis systolic multiplier over Galois field GF(2m) using Hankel matrix and Karatsuba algorithm. IET Inf. Secur. 7(2) (2013) - [j32]Jeng-Shyang Pan
Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3195-3204 (2013) - [c23]Chiou-Yng Lee, Wen-Yo Lee, Che Wun Chiou, Jeng-Shyang Pan
Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m ). ICGEC 2013: 359-368 - [c22]Che Wun Chiou, Jim-Min Lin, Yu-Ku Li, Chiou-Yng Lee, Tai-Pao Chuang, Yun-Chi Yeh:
Pipeline Design of Bit-Parallel Gaussian Normal Basis Multiplier over GF(2m). ICGEC 2013: 369-377 - [c21]Chun-Sheng Yang, Jeng-Shyang Pan
Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m). RVSP 2013: 123-128 - 2012
- [j31]Tai-Pao Chuang, Che Wun Chiou, Shun-Shii Lin, Chiou-Yng Lee
Fault-tolerant Gaussian normal basis multiplier over GF(2m). IET Inf. Secur. 6(3): 157-170 (2012) - [j30]Che Wun Chiou, Hung Wei Chang, Wen-Yew Liang, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh:
Low-complexity Gaussian normal basis multiplier over GF(2m). IET Inf. Secur. 6(4): 310-317 (2012) - [j29]Che Wun Chiou, Tai-Pao Chuang, Shun-Shii Lin, Chiou-Yng Lee, Jim-Min Lin, Yun-Chi Yeh:
Palindromic-like representation for Gaussian normal basis multiplier over GF(2m) with odd type t. IET Inf. Secur. 6(4): 318-323 (2012) - [j28]Chiou-Yng Lee
Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation. J. Signal Process. Syst. 69(2): 197-211 (2012) - [c20]Chiou-Yng Lee
Super Digit-Serial Systolic Multiplier over GF(2^m). ICGEC 2012: 509-513 - [c19]Liang-Hwa Chen, Po-Lun Chang, Yen-Ching Chang, Chiou-Yng Lee
A Scalable Architecture for Dual Basis GF(2m) Multiplications. ISBAST 2012: 45-50 - 2011
- [j27]Chiou-Yng Lee
Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2m). Int. J. Auton. Adapt. Commun. Syst. 4(3): 291-306 (2011) - [j26]Che Wun Chiou, Chiou-Yng Lee
Multiplexer implementation of low-complexity polynomial basis multiplier in GF(m2) using all one polynomial. Inf. Process. Lett. 111(21-22): 1044-1047 (2011) - [c18]Chiou-Yng Lee
Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. ICGEC 2011: 232-236 - [c17]Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee
Novel Mastrovito Multiplier over GF(2m) Using Trinomial. ICGEC 2011: 237-242 - 2010
- [j25]Chiou-Yng Lee
Efficient bit-parallel multipliers over finite fields GF(2m). Comput. Electr. Eng. 36(5): 955-968 (2010) - [j24]Che Wun Chiou, Wen-Yew Liang, Hung Wei Chang, Jim-Min Lin, Chiou-Yng Lee
Concurrent error detection in semi-systolic dual basis multiplier over GF(2m) using self-checking alternating logic. IET Circuits Devices Syst. 4(5): 382-391 (2010) - [j23]Chiou-Yng Lee
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m). Integr. 43(1): 113-123 (2010) - [j22]Chiou-Yng Lee
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1234-1238 (2010) - [j21]Chiou-Yng Lee
Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme. J. Signal Process. Syst. 58(2): 233-246 (2010) - [c16]Chiou-Yng Lee
Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach. AINA Workshops 2010: 234-239 - [c15]Chiou-Yng Lee
Concurrent Error Detection in Systolic Array AB^2 Multiplier Using Linear Codes. CASoN 2010: 111-115 - [c14]Che Wun Chiou, Jim-Min Lin, Chiou-Yng Lee
Fast Optimal Normal Basis Multiplier with Type-2kw Over GF (2m). CASoN 2010: 116-120 - [c13]Chiou-Yng Lee
Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2m). ISPA 2010: 405-412
2000 – 2009
- 2009
- [j20]Che Wun Chiou, Chiou-Yng Lee
Concurrent error detection and correction in dual basis multiplier over GF(2m). IET Circuits Devices Syst. 3(1): 22-40 (2009) - [j19]Che Wun Chiou, Chiou-Yng Lee
Unified dual-field multiplier in GF(P) and GF(2k). IET Inf. Secur. 3(2): 45-52 (2009) - [j18]Che Wun Chiou, Chin-Chen Chang, Chiou-Yng Lee
Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m). IEEE Trans. Computers 58(6): 851-857 (2009) - [c12]Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 - [c11]Pramod Kumar Meher, Chiou-Yng Lee
Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. ISCAS 2009: 2910-2913 - [c10]Wen-Yo Lee, Jhu-Syuan Guo, Chiou-Yng Lee
Implementation of an interactive mobile robot over mixed reality. ROBIO 2009: 80-85 - 2008
- [j17]Chiou-Yng Lee
Multiplexer-based bit-parallel systolic multipliers over GF(2m). Comput. Electr. Eng. 34(5): 392-405 (2008) - [j16]Chiou-Yng Lee
Low-Complexity Parallel Systolic Montgomery Multipliers over GF(2m) Using Toeplitz Matrix-Vector Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(6): 1470-1477 (2008) - [j15]Chin-Chin Chen, Chiou-Yng Lee
Scalable and Systolic Montgomery Multipliers over GF(2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(7): 1763-1771 (2008) - [j14]Chiou-Yng Lee
Low-complexity bit-parallel systolic multipliers over GF(2m). Integr. 41(1): 106-112 (2008) - [j13]Chiou-Yng Lee
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. J. Signal Process. Syst. 52(3): 313-324 (2008) - [c9]Chiou-Yng Lee
Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m). AINA Workshops 2008: 1499-1504 - [c8]Chiou-Yng Lee
Efficient Bit-Parallel Multipliers in Composite Fields. APSCC 2008: 686-691 - [c7]Chin-Chin Chen, Chiou-Yng Lee
Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m). Mobility Conference 2008: 46 - 2007
- [j12]Chiou-Yng Lee
Scalable and systolic Montgomery multiplier over GF(2m) generated by trinomials. IET Circuits Devices Syst. 1(6): 477-484 (2007) - [j11]Chiou-Yng Lee
Unified Parallel Systolic Multiplier Over GF(2m). J. Comput. Sci. Technol. 22(1): 28-38 (2007) - [c6]Chiou-Yng Lee, Yung-Hui Chen:
Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2m). AINA Workshops (1) 2007: 906-911 - 2006
- [j10]Chiou-Yng Lee
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m). J. Electron. Test. 22(2): 143-150 (2006) - [j9]Che Wun Chiou, Chiou-Yng Lee, An-Wen Deng, Jim-Min Lin:
Concurrent Error Detection in Montgomery Multiplication over GF(2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 566-574 (2006) - [j8]Chiou-Yng Lee
Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation. J. Comput. Sci. Technol. 21(6): 887-892 (2006) - [c5]Chiou-Yng Lee
New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm. APCCAS 2006: 610-613 - [c4]Chiou-Yng Lee
Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). SMC 2006: 1160-1165 - 2005
- [j7]Chiou-Yng Lee
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm. Comput. Electr. Eng. 31(7): 444-459 (2005) - [j6]Che Wun Chiou, Chiou-Yng Lee
Multiplexer-based double-exponentiation for normal basis of GF(2m). Comput. Secur. 24(1): 83-86 (2005) - [j5]Chiou-Yng Lee
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m). J. Electron. Test. 21(5): 539-549 (2005) - [j4]Chiou-Yng Lee
Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2m). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3169-3179 (2005) - [j3]Chiou-Yng Lee, Jenn-Shyong Horng, I-Chang Jou, Erl-Huei Lu:
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2m). IEEE Trans. Computers 54(9): 1061-1070 (2005) - 2004
- [c3]Chiou-Yng Lee, Chung-Jyi Chang:
Low-complexity linear array multiplier for normal basis of type-II. ICME 2004: 1515-1518 - 2003
- [j2]Chiou-Yng Lee:
Low-Latency Bit-Parallel Systolic Multiplier for Irreducible xm + xn + 1 with GCD(m, n) = 1. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(11): 2844-2852 (2003) - 2002
- [c2]Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu:
Low-complexity systolic multiplier over GF(2m) using weakly dual basis. APCCAS (1) 2002: 367-372 - 2001
- [j1]Chiou-Yng Lee
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. IEEE Trans. Computers 50(5): 385-393 (2001) - [c1]Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee:
New bit-parallel systolic multipliers for a class of GF(2m). ISCAS (4) 2001: 578-581
Coauthor Index
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