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Li Jiang 0002
蒋力
Person information
- unicode name: 蒋力
- affiliation: Shanghai Jiao Tong University, Department of Computer Science and Engineering, China
- affiliation (PhD 2013): Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong
Other persons with the same name
- Li Jiang — disambiguation page
- Li Jiang 0001
— Harbin Institute of Technology, State Key Laboratory of Robotics and System, China
- Li Jiang 0003
- Li Jiang 0004
- Li Jiang 0005
- Li Jiang 0006 — Joint Operations Division, Canberra, Australia (and 2 more)
- Li Jiang 0007 — Robert Bosch LLC, Department of Gasoline System Engineering, Farmington Hills, MI, USA
- Li Jiang 0008 — Tsinghua University, Tsinghua-Berkeley Shenzhen Institute, TBSI, China
- Li Jiang 0009
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2020 – today
- 2025
- [j26]Shiyuan Huang
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization. ACM Trans. Design Autom. Electr. Syst. 30(1): 1-22 (2025) - 2024
- [j25]Fangxin Liu
ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity. IEEE Trans. Computers 73(9): 2320-2334 (2024) - [j24]Chen Nie
VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations. IEEE Trans. Computers 73(10): 2378-2390 (2024) - [c92]Fangxin Liu, Haomin Li
PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing. ASPDAC 2024: 46-51 - [c91]Haomin Li
HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing. ASPDAC 2024: 716-721 - [c90]Fangxin Liu, Haomin Li
TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks. ASPDAC 2024: 842-847 - [c89]Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li
TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation. ASPDAC 2024: 884-889 - [c88]Fangxin Liu
INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding. DAC 2024: 10:1-10:6 - [c87]Ning Yang
EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks. DAC 2024: 58:1-58:6 - [c86]Jiahao Sun, Fangxin Liu, Yijian Zhang, Li Jiang, Rui Yang:
RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 µs Collision Detection. DATE 2024: 1-2 - [c85]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, Xiaoyao Liang:
Watt: A Write-Optimized RRAM-Based Accelerator for Attention. Euro-Par (2) 2024: 107-120 - [c84]Fangxin Liu, Ning Yang, Haomin Li
SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding. HPCA 2024: 1029-1042 - [c83]Yilong Zhao
UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space. ISCA 2024: 644-659 - [c82]Fangxin Liu
LowPASS: A Low power PIM-based accelerator with Speculative Scheme for SNNs. ISLPED 2024: 1-6 - [c81]Zhuoran Song, Houshu He, Fangxin Liu, Yifan Hao, Xinkai Song, Li Jiang, Xiaoyao Liang:
SRender: Boosting Neural Radiance Field Efficiency via Sensitivity-Aware Dynamic Precision Rendering. MICRO 2024: 525-537 - [c80]Zongwu Wang, Fangxin Liu, Ning Yang, Shiyuan Huang, Haomin Li, Li Jiang:
COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with Adaptive Spike Speculation. MICRO 2024: 1090-1106 - 2023
- [j23]Tao Yang
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 150-163 (2023) - [j22]Fangxin Liu
SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 204-217 (2023) - [j21]Tao Yang
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 509-520 (2023) - [j20]Zhuoran Song
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2238-2251 (2023) - [c79]Fangxin Liu, Haoming Li
HyperAttack: An Efficient Attack Framework for HyperDimensional Computing. DAC 2023: 1-6 - [c78]Tao Yang, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao, Li Jiang:
SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication. DAC 2023: 1-6 - [c77]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, Li Jiang:
SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration. DATE 2023: 1-2 - [c76]Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. DATE 2023: 1-6 - [c75]Tao Yang, Hui Ma, Yilong Zhao
PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy. DATE 2023: 1-6 - [c74]Haomin Li
HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing. ICCAD 2023: 1-9 - [c73]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model. ICCD 2023: 375-382 - [c72]Fangxin Liu, Ning Yang, Li Jiang:
PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture. ICCD 2023: 507-514 - [c71]Yaoyao Ye
ASDR: An Application-Specific Deadlock-Free Routing for Chiplet-Based Systems. NoCArc@MICRO 2023: 46-51 - 2022
- [j19]Weidong Cao
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. IEEE Trans. Computers 71(9): 2142-2155 (2022) - [j18]Fangxin Liu
IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5313-5326 (2022) - [c70]Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Li Jiang:
SpikeConverter: An Efficient Conversion Framework Zipping the Gap between Artificial Neural Networks and Spiking Neural Networks. AAAI 2022: 1692-1701 - [c69]Qidong Tang, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, Li Jiang:
HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine. ASP-DAC 2022: 226-231 - [c68]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. DAC 2022: 259-264 - [c67]Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, Li Jiang:
PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration. DAC 2022: 1087-1092 - [c66]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, Li Jiang:
SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture. DAC 2022: 1105-1110 - [c65]Tao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, Li Jiang:
DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture. DATE 2022: 700-705 - [c64]Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia
Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing. DATE 2022: 1251-1256 - [c63]Yu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, Li Jiang:
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores. FPGA 2022: 112-122 - [c62]Fangxin Liu, Zongwu Wang, Wenbo Zhao, Yongbiao Chen, Tao Yang, Xiaokang Yang, Li Jiang:
Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs. ICCD 2022: 451-454 - [c61]Chen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, Zhezhi He:
Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System. ISQED 2022: 1-6 - [c60]Fangxin Liu, Haomin Li
L3E-HD: A Framework Enabling Efficient Ensemble in High-Dimensional Space for Language Tasks. SIGIR 2022: 1844-1848 - [i14]Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, Li Jiang:
Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals. CoRR abs/2201.12861 (2022) - [i13]Zhuoran Song, Yihong Xu, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction. CoRR abs/2203.04570 (2022) - [i12]Zhuoran Song, Yihong Xu, Han Li, Naifeng Jing, Xiaoyao Liang, Li Jiang:
DNN Training Acceleration via Exploring GPGPU Friendly Sparsity. CoRR abs/2203.05705 (2022) - [i11]Yilong Zhao
RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN. CoRR abs/2210.15255 (2022) - 2021
- [j17]Zhuoran Song
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 129-142 (2021) - [j16]Yanan Sun
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2495-2507 (2021) - [j15]Tao Yang, Zhezhi He, Tengchuan Kou, Qingzheng Li, Qi Han, Haibao Yu, Fangxin Liu, Yun Liang, Li Jiang:
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization. ACM Trans. Reconfigurable Technol. Syst. 14(4): 18:1-18:28 (2021) - [j14]Hongtao Zhong
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1981-1993 (2021) - [c59]Yunyan Hong, Ailing Zeng, Min Li, Cewu Lu, Li Jiang, Qiang Xu
Skimming and Scanning for Efficient Action Recognition in Untrimmed Videos. CISP-BMEI 2021: 1-10 - [c58]Dongyue Li, Tao Yang, Lun Du
AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs. CIKM 2021: 3206-3210 - [c57]Hanchen Guo, Zhehan Lin, Yunfei Gu, Chentao Wu, Li Jiang, Jie Li, Guangtao Xue, Minyi Guo:
Lazy-WL: A Wear-aware Load Balanced Data Redistribution Method for Efficient SSD Array Scaling. CLUSTER 2021: 157-168 - [c56]Min Li, Yu Li, Ye Tian, Li Jiang, Qiang Xu
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference. DAC 2021: 409-414 - [c55]Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao
PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration. DAC 2021: 583-588 - [c54]Ziqi Meng, Weikang Qian, Yilong Zhao, Yanan Sun, Rui Yang, Li Jiang:
Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation. DATE 2021: 1078-1083 - [c53]Yilong Zhao
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. ACM Great Lakes Symposium on VLSI 2021: 15-20 - [c52]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Tao Yang, Li Jiang:
IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration. ACM Great Lakes Symposium on VLSI 2021: 253-258 - [c51]Chen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, Zhezhi He:
Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support. ACM Great Lakes Symposium on VLSI 2021: 347-352 - [c50]Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang:
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator. ICCAD 2021: 1-9 - [c49]Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, Li Jiang:
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. ICCD 2021: 417-424 - [c48]Fangxin Liu, Wenbo Zhao, Zhezhi He, Yanzhi Wang, Zongwu Wang, Changzhi Dai, Xiaoyao Liang, Li Jiang:
Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point. ICCV 2021: 5261-5270 - [c47]Tianhong Shen, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, Li Jiang:
A Ternary Memristive Logic-in-Memory Design for Fast Data Scan. ICTA 2021: 183-184 - [c46]Zhuoran Song, Dongyue Li, Zhezhi He, Xiaoyao Liang, Li Jiang:
ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator. ISCAS 2021: 1-5 - [c45]Feiyang Wu, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PIPArch: Programmable Image Processing Architecture Using Sliding Array. ISPA/BDCloud/SocialCom/SustainCom 2021: 73-80 - [c44]Xingyi Wang, Yu Li, Yiquan Chen
On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers. VTS 2021: 1-6 - [i10]Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. CoRR abs/2103.01705 (2021) - [i9]Yunyan Hong, Ailing Zeng, Min Li, Cewu Lu, Li Jiang, Qiang Xu:
Skimming and Scanning for Untrimmed Video Action Recognition. CoRR abs/2104.10492 (2021) - [i8]Min Li, Yu Li, Ye Tian, Li Jiang, Qiang Xu:
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference. CoRR abs/2105.04104 (2021) - [i7]Yu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, Li Jiang:
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores. CoRR abs/2112.08193 (2021) - 2020
- [j13]Qi Yan
Measurement Scheduling for Cooperative Localization in Resource-Constrained Conditions. IEEE Robotics Autom. Lett. 5(2): 1991-1998 (2020) - [c43]Chaoqun Chu, Yanzhi Wang, Yilong Zhao
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. DAC 2020: 1-6 - [c42]Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. DAC 2020: 1-6 - [c41]Chang Ma
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing. DATE 2020: 1432-1437 - [c40]Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang:
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. FPL 2020: 254-261 - [c39]Zhuoran Song, Yilong Zhao
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory. ACM Great Lakes Symposium on VLSI 2020: 291-296 - [c38]Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, Xiaoyao Liang:
DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration. ISCA 2020: 1010-1021 - [c37]Xingyi Wang, Li Jiang, Krishnendu Chakrabarty
LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection. VTS 2020: 1-6 - [i6]Fangxin Liu, Wenbo Zhao, Yanzhi Wang, Changzhi Dai, Li Jiang:
AUSN: Approximately Uniform Quantization by Adaptively Superimposing Non-uniform Distribution for Deep Neural Networks. CoRR abs/2007.03903 (2020)
2010 – 2019
- 2019
- [j12]Yanan Sun
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 753-757 (2019) - [j11]Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method. ACM Trans. Design Autom. Electr. Syst. 24(6): 59:1-59:25 (2019) - [c36]Houxiang Ji
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. ASP-DAC 2019: 249-254 - [c35]Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
A sharing-aware L1.5D cache for data reuse in GPGPUs. ASP-DAC 2019: 388-393 - [c34]Xiaoyi Sun, Krishnendu Chakrabarty
System-level hardware failure prediction using deep learning. DAC 2019: 20 - [c33]Zhuoran Song, Ru Wang
Approximate Random Dropout for DNN training acceleration in GPGPU. DATE 2019: 108-113 - [c32]Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, Yanzhi Wang:
An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM. ISLPED 2019: 1-6 - [i5]Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, Yanzhi Wang:
An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM. CoRR abs/1908.11691 (2019) - [i4]Qi Yan, Li Jiang, Solmaz S. Kia:
Measurement Scheduling for Cooperative Localization in Resource-constrained Conditions. CoRR abs/1912.04709 (2019) - 2018
- [j10]Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim
CNFET-Based High Throughput SIMD Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1331-1344 (2018) - [j9]Chen Wang, Yanan Sun, Shiyan Hu, Li Jiang, Weikang Qian:
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit. ACM Trans. Design Autom. Electr. Syst. 23(4): 44:1-44:27 (2018) - [j8]Jianfei Wang
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. IEEE Trans. Parallel Distributed Syst. 29(3): 586-599 (2018) - [c31]Houxiang Ji
ReCom: An efficient resistive accelerator for compressed deep neural networks. DATE 2018: 237-240 - [c30]Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim
In-growth test for monolithic 3D integrated SRAM. DATE 2018: 569-572 - [c29]Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang:
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). FPGA 2018: 286 - [c28]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: approximate computing using an end-to-end trainable neural network. ICCAD 2018: 11:1-11:8 - [c27]Haiyue Song, Chengwen Xu, Qiang Xu
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. ICCAD 2018: 50 - [i3]Zhuoran Song, Dongyu Ru, Ru Wang, Hongru Huang, Zhenghao Peng, Jing Ke, Xiaoyao Liang, Li Jiang:
Approximate Random Dropout. CoRR abs/1805.08939 (2018) - [i2]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: ApproXimate computing using an end-to-end trainable neural network. CoRR abs/1807.10458 (2018) - [i1]Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators. CoRR abs/1810.08379 (2018) - 2017
- [j7]Jianfei Wang
Incorporating selective victim cache into GPGPU for high-performance computing. Concurr. Comput. Pract. Exp. 29(24) (2017) - [j6]Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 520-533 (2017) - [c26]Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. DAC 2017: 38:1-38:6 - [c25]Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu
On Quality Trade-off Control for Approximate Computing Using Iterative Training. DAC 2017: 52:1-52:6 - [c24]Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, Li Jiang:
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar. DATE 2017: 19-24 - [c23]Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang:
Fault clustering technique for 3D memory BISR. DATE 2017: 560-565 - 2016
- [j5]Naifeng Jing, Li Jiang, Tao Zhang
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs. IEEE Trans. Computers 65(1): 122-135 (2016) - [j4]Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1192-1205 (2016) - [c22]Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang:
CNFET-based high throughput register file architecture. ICCD 2016: 662-669 - [c21]Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, Naifeng Jing:
Applying Victim Cache in High Performance GPGPU Computing. ISPDC 2016: 24-29 - [c20]Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu
Defect tolerance for CNFET-based SRAMs. ITC 2016: 1-9 - [c19]Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang:
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. MICRO 2016: 14:1-14:12 - 2015
- [j3]Xiaolong Zhang, Huiyun Li, Li Jiang, Qiang Xu:
A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2639-2647 (2015) - [c18]Zelong Sun, Li Jiang, Qiang Xu
On test syndrome merging for reasoning-based board-level functional fault diagnosis. ASP-DAC 2015: 737-742 - [c17]Feng Xie, Xiaoyao Liang, Qiang Xu
Jump test for metallic CNTs in CNFET-based SRAM. DAC 2015: 16:1-16:6 - [c16]Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu
A novel TSV probing technique with adhesive test interposer. ICCD 2015: 597-604 - [c15]Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, Xiaoyao Liang:
Building Fuel Powered Supercomputing Data Center at Low Cost. ICS 2015: 241-250 - [c14]Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank stealing for conflict mitigation in GPGPU Register File. ISLPED 2015: 55-60 - [c13]Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. ITC 2015: 1-10 - [c12]Li Jiang, Qiang Xu
Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist. ITC 2015: 1-11 - [c11]Li Jiang, Qiang Xu
Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges. NOCS 2015: 7:1-7:8 - [c10]Tianjian Li, Hao Chen
On microarchitectural modeling for CNFET-based circuits. SoCC 2015: 356-361 - [c9]Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian:
Timing-driven placement for carbon nanotube circuits. SoCC 2015: 362-367 - 2013
- [j2]Li Jiang, Qiang Xu
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 559-571 (2013) - [c8]Li Jiang, Fangming Ye, Qiang Xu
On effective and efficient in-field TSV repair for stacked 3D ICs. DAC 2013: 74:1-74:6 - [c7]Zelong Sun, Li Jiang, Qiang Xu
AgentDiag: An agent-assisted diagnostic framework for board-level functional failures. ITC 2013: 1-8 - 2012
- [j1]Li Jiang, Qiang Xu
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1621-1633 (2012) - [c6]Qiang Xu
Yield enhancement for 3D-stacked ICs: Recent advances and challenges. ASP-DAC 2012: 731-737 - [c5]Li Jiang, Qiang Xu, Bill Eklow:
On effective TSV repair for 3D-stacked ICs. DATE 2012: 793-798 - 2010
- [c4]Li Jiang, Rong Ye, Qiang Xu
Yield enhancement for 3D-stacked memory by redundancy sharing across dies. ICCAD 2010: 230-234 - [c3]Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu
Modeling TSV open defects in 3D-stacked DRAM. ITC 2010: 174-182
2000 – 2009
- 2009
- [c2]Li Jiang, Lin Huang, Qiang Xu:
Test architecture design and optimization for three-dimensional SoCs. DATE 2009: 220-225 - [c1]Li Jiang, Qiang Xu
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD 2009: 191-196
Coauthor Index
[j25] [j24] [c85] [c83] [c81] [j22] [j20] [c76] [c73] [c68] [c63] [i13] [i12] [i11] [j17] [c55] [c53] [c51] [c49] [c48] [c46] [c45] [i10] [i7] [c43] [c42] [c39] [c38] [j11] [c36] [c35] [c34] [c33] [j10] [j8] [c30] [c29] [c28] [c27] [i3] [i2] [i1] [j7] [j6] [c26] [c25] [c24] [c23] [j5] [j4] [c22] [c21] [c20] [c19] [c17] [c16] [c15] [c14] [c13] [c10] [c9]
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