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Kaushik Ravindran
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2010 – 2019
- 2016
- [j2]Stavros Tripakis
, Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang, Hugo A. Andrade, Arkadeb Ghosal:
Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware. J. Signal Process. Syst. 85(1): 23-43 (2016) - [c16]Patricia Derler
Specification of precise timing in synchronous dataflow models. MEMOCODE 2016: 85-94 - [r2]Kurt Keutzer, Kaushik Ravindran:
Technology Mapping. Encyclopedia of Algorithms 2016: 2200-2204 - 2014
- [c15]Stavros Tripakis
On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations. ICSAMOS 2014: 51-58 - [p1]Kaushik Ravindran, Arkadeb Ghosal, Rhishikesh Limaye, Douglas Kim, Hugo A. Andrade, Jeff Correll, Jacob Kornerup, Ian C. Wong, Gerald Wang, Guang Yang, Amal Ekbal, Mike Trimborn, Ankita Prasad, Trung N. Tran:
Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets. Embedded Systems Development, From Functional Models to Implementations 2014: 19-39 - 2012
- [c14]Arkadeb Ghosal, Rhishikesh Limaye, Kaushik Ravindran, Stavros Tripakis
Static dataflow with access patterns: semantics and analysis. DAC 2012: 656-663 - [c13]Kaushik Ravindran, Arkadeb Ghosal, Rhishikesh Limaye, Hugo A. Andrade, Alejandro Asenjo, Takao Inoue, Douglas Kim, Ankita Prasad, Trung N. Tran, Mike Trimborn, Guoqiang Wang, Guang Yang:
Tools for deploying dataflow models on FPGA targets. DASIP 2012: 1-2 - [c12]Kaushik Ravindran, Arkadeb Ghosal, Rhishikesh Limaye, Guoqiang Wang, Guang Yang, Hugo A. Andrade:
Analysis techniques for static dataflow models with access patterns. DASIP 2012: 1-8 - [c11]Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang:
Early timing estimation for system-level design using FPGAs (abstract only). FPGA 2012: 271 - [c10]Hugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans:
A methodology for the design and deployment of reliable systems on heterogeneous platforms. ReConFig 2012: 1-7 - 2011
- [c9]Stavros Tripakis
Correct and non-defensive glue design using abstract models. CODES+ISSS 2011: 59-68
2000 – 2009
- 2009
- [c8]Samah Abu-Mahmeed, Cheryl McCosh, Zoran Budimlic, Ken Kennedy, Kaushik Ravindran, Kevin Hogan, Paul Austin, Steve Rogers, Jacob Kornerup:
Scheduling Tasks to Maximize Usage of Aggregate Variables in Place. CC 2009: 204-219 - 2008
- [c7]Nadathur Satish, Kaushik Ravindran, Kurt Keutzer:
Scheduling task dependence graphs with variable task execution times onto heterogeneous multiprocessors. EMSOFT 2008: 149-158 - [r1]Kurt Keutzer, Kaushik Ravindran:
Technology Mapping. Encyclopedia of Algorithms 2008 - 2007
- [c6]Nadathur Satish, Kaushik Ravindran, Kurt Keutzer:
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. DATE 2007: 57-62 - [c5]Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer:
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling. ICME 2007: 1874-1877 - 2005
- [c4]Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer:
An automated exploration framework for FPGA-based soft multiprocessor systems. CODES+ISSS 2005: 273-278 - [c3]Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer:
Soft multiprocessor systems for network applications (abstract only). FPGA 2005: 271 - [c2]Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer:
An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. FPL 2005: 487-492 - 2004
- [j1]Niraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer:
NP-Click: A Productive Software Development Approach for Network Processors. IEEE Micro 24(5): 45-54 (2004) - 2003
- [c1]Kaushik Ravindran, Andreas Kuehlmann, Ellen Sentovich:
Multi-Domain Clock Skew Scheduling. ICCAD 2003: 801-808
Coauthor Index
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