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Ioannis Savidis
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2020 – today
- 2024
- [c64]Pratik Shrestha
, Alec Aversa
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation. ACM Great Lakes Symposium on VLSI 2024: 69-77 - [c63]Alec Aversa
Harnessing Heterogeneity for Targeted Attacks on 3-D ICs. ACM Great Lakes Symposium on VLSI 2024: 246-251 - [c62]Ziyi Chen, Ioannis Savidis:
Block Configuration Algorithms for a Reconfigurable Analog Array. ISCAS 2024: 1-5 - [c61]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
DNA: DC Nodal Analysis Attack for Analog Circuits. ISCAS 2024: 1-5 - [c60]Zhengfeng Wu, Ioannis Savidis:
Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits. ISCAS 2024: 1-5 - [c59]Pratik Shrestha, Ioannis Savidis:
EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation. ISQED 2024: 1-7 - [c58]Zhengfeng Wu, Ioannis Savidis:
Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling. ISQED 2024: 1-7 - 2023
- [j21]Vaibhav Venugopal Rao
Hidden Costs of Analog Deobfuscation Attacks. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1802-1815 (2023) - [c57]Ziyi Chen, Ioannis Savidis:
A Power Side-Channel Attack on Flash ADC. ISCAS 2023: 1-5 - [c56]Pratik Shrestha, Ioannis Savidis:
Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect. ISCAS 2023: 1-5 - [c55]Zhengfeng Wu, Ioannis Savidis:
Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies. ISCAS 2023: 1-5 - [c54]Zhengfeng Wu, Isabel Song, Ioannis Savidis:
Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation. MLCAD 2023: 1-6 - 2022
- [c53]Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Sayed Aresh Beheshti-Shirazi, Ali Mirzaeian, Xiaojie Guo, Sai Manoj P. D., Houman Homayoun, Ioannis Savidis, Liang Zhao, Avesta Sasan:
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis. ACM Great Lakes Symposium on VLSI 2022: 493-500 - [c52]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Practical Performance of Analog Attack Techniques. HOST 2022: 153-156 - [c51]Zhengfeng Wu, Ioannis Savidis:
Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes. ISCAS 2022: 1033-1037 - [c50]Ziyi Chen, Ioannis Savidis:
Reconfigurable Analog Array for Hardware Security. ISCAS 2022: 1047-1051 - [c49]Pratik Shrestha, Ioannis Savidis:
Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking. ISCAS 2022: 1734-1738 - [c48]Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis:
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. ISQED 2022: 1-7 - [c47]Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan:
Adaptive-Gravity: A Defense Against Adversarial Samples. ISQED 2022: 96-101 - [c46]Pratik Shrestha, Saran Phatharodom, Ioannis Savidis:
Graph Representation Learning for Gate Arrival Time Prediction. MLCAD 2022: 127-133 - [c45]Zhengfeng Wu, Ioannis Savidis:
Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks. MLCAD 2022: 159-165 - [e2]Ioannis Savidis, Avesta Sasan, Himanshu Thapliyal, Ronald F. DeMara:
GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022. ACM 2022, ISBN 978-1-4503-9322-5 [contents] - [i1]Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan:
Adaptive-Gravity: A Defense Against Adversarial Samples. CoRR abs/2204.03694 (2022) - 2021
- [j20]Md Shazzad Hossain
Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 762-775 (2021) - [j19]Kyle Juretus
Synthesis of Hidden State Transitions for Sequential Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 11-23 (2021) - [j18]Kyle Juretus
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 38-51 (2021) - [j17]Vaibhav Venugopal Rao
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2013-2026 (2021) - [c44]Md Shazzad Hossain
Energy Efficient Computing with Heterogeneous DNN Accelerators. AICAS 2021: 1-4 - [c43]Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, Avesta Sasan:
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop. ACM Great Lakes Symposium on VLSI 2021: 181-187 - [c42]Saran Phatharodom, Avesta Sasan, Ioannis Savidis:
SAT-attack Resilience Measure for Access Restricted Circuits. ACM Great Lakes Symposium on VLSI 2021: 213-220 - [c41]Ziyi Chen, Ioannis Savidis:
Reconfigurable Array for Analog Applications. ICCD 2021: 361-365 - [c40]Zhengfeng Wu, Ioannis Savidis:
Variation-aware Analog Circuit Sizing with Classifier Chains. MLCAD 2021: 1-6 - [e1]Yiran Chen, Victor V. Zhirnov, Avesta Sasan, Ioannis Savidis:
GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021. ACM 2021, ISBN 978-1-4503-8393-6 [contents] - 2020
- [j16]Marko Jacovic
Physical Layer Encryption for Wireless OFDM Communication Systems. J. Hardw. Syst. Secur. 4(3): 230-245 (2020) - [j15]Md Shazzad Hossain
Recycling of unused leakage current for energy efficient multi-voltage systems. Microelectron. J. 101: 104782 (2020) - [j14]Md Shazzad Hossain
Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing. Microelectron. J. 102: 104801 (2020) - [j13]Kyle Juretus
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1607-1620 (2020) - [c39]Kyle Juretus, Ioannis Savidis:
Reducing Logic Locking Key Leakage through the Scan Chain. ISCAS 2020: 1-5 - [c38]Saran Phatharodom, Nagarajan Kandasamy, Ioannis Savidis:
Modeling SAT-Attack Search Complexity. ISCAS 2020: 1-5 - [c37]Vaibhav Venugopal Rao, Kyle Juretus, Ioannis Savidis:
Security Vulnerabilities of Obfuscated Analog Circuits. ISCAS 2020: 1-5 - [c36]Md Shazzad Hossain, Ioannis Savidis:
Dynamic idle core management and leakage current reuse in MPSoC platforms. ISLPED 2020: 49-54 - [c35]Zhengfeng Wu, Ioannis Savidis:
CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing. MLCAD 2020: 49-54
2010 – 2019
- 2019
- [j12]James Chacko, Kyle Juretus
Securing Wireless Communication via Hardware-Based Packet Obfuscation. J. Hardw. Syst. Secur. 3(3): 261-272 (2019) - [j11]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c34]Kyle Juretus, Vaibhav Venugopal Rao, Ioannis Savidis:
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. ACM Great Lakes Symposium on VLSI 2019: 483-488 - [c33]Divya Pathak, Ioannis Savidis:
Applying Swarm Intelligence to Distributed On-Chip Power Management. ICCD 2019: 532-540 - [c32]Md Shazzad Hossain
Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems. ISCAS 2019: 1-5 - [c31]Kyle Juretus, Ioannis Savidis:
Increasing the SAT Attack Resiliency of In-Cone Logic Locking. ISCAS 2019: 1-5 - [c30]Vaibhav Venugopal Rao, Ioannis Savidis:
Mesh Based Obfuscation of Analog Circuit Properties. ISCAS 2019: 1-5 - [c29]Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis:
Robust Low Power Clock Synchronization for Multi-Die Systems. ISLPED 2019: 1-6 - 2018
- [j10]Mohammad Khavari Tavana
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 249-261 (2018) - [j9]Divya Pathak
On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2230-2240 (2018) - [c28]Vaibhav Venugopal Rao, Ioannis Savidis:
Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory. APCCAS 2018: 102-106 - [c27]Kyle Juretus, Ioannis Savidis:
Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. APCCAS 2018: 366-369 - [c26]Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun:
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning. ASP-DAC 2018: 70-75 - [c25]Ioannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin:
Securing the Systems of the Future - Techniques for a Shifting Attack Space. ACM Great Lakes Symposium on VLSI 2018: 517 - [c24]Md Shazzad Hossain, Ioannis Savidis:
Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery. IGSC 2018: 1-8 - [c23]David Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead:
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. ICCD 2018: 83-91 - [c22]Md Shazzad Hossain
Noise Constrained Optimum Selection of Supply Voltage for IoT Applications. ISCAS 2018: 1-5 - [c21]Kyle Juretus, Ioannis Savidis:
Time Domain Sequential Locking for Increased Security. ISCAS 2018: 1-5 - 2017
- [j8]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j7]Divya Pathak
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2538-2551 (2017) - [c20]Divya Pathak, Houman Homayoun, Ioannis Savidis:
Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery. ACM Great Lakes Symposium on VLSI 2017: 387-392 - [c19]Vaibhav Venugopal Rao, Ioannis Savidis:
Parameter biasing obfuscation for analog IP protection. HOST 2017: 161 - [c18]James Chacko, Kyle Juretus, Marko Jacovic, Cem Sahin, Nagarajan Kandasamy, Ioannis Savidis, Kapil R. Dandekar
Physical gate based preamble obfuscation for securing wireless communication. ICNC 2017: 293-297 - [c17]Vaibhav Venugopal Rao, Ioannis Savidis:
Protecting analog circuits with parameter biasing obfuscation. LATS 2017: 1-6 - [c16]Md Shazzad Hossain
Bi-directional input/output circuits with integrated level shifters for near-threshold computing. MWSCAS 2017: 1240-1243 - [c15]Isuru Daulagala, Ioannis Savidis:
Clock tree synthesis for heterogeneous 3-D integrated circuits. SLIP 2017: 1-6 - 2016
- [j6]Ioannis Savidis
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. Microelectron. J. 50: 66-75 (2016) - [c14]Kyle Juretus, Ioannis Savidis:
Reduced Overhead Gate Level Logic Encryption. ACM Great Lakes Symposium on VLSI 2016: 15-20 - [c13]Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana
Load Balanced On-Chip Power Delivery for Average Current Demand. ACM Great Lakes Symposium on VLSI 2016: 439-444 - [c12]Md Shazzad Hossain
Robust near-threshold inverter with improved performance for ultra-low power applications. ISCAS 2016: 738-741 - [c11]Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana
Energy efficient on-chip power delivery with run-time voltage regulator clustering. ISCAS 2016: 1210-1213 - [c10]Kyle Juretus, Ioannis Savidis:
Reducing logic encryption overhead through gate level key insertion. ISCAS 2016: 1714-1717 - [c9]Kostas Siozios
A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. SAMOS 2016: 336-341 - 2015
- [j5]Ioannis Savidis, Boris Vaisband, Eby G. Friedman:
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2077-2089 (2015) - [c8]Mohammad Khavari Tavana
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling. DAC 2015: 151:1-151:6 - [c7]Mohammad Khavari Tavana
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping. ICCD 2015: 581-588 - 2014
- [c6]Boris Vaisband, Ioannis Savidis, Eby G. Friedman:
Thermal conduction path analysis in 3-D ICs. ISCAS 2014: 594-597 - [c5]Divya Pathak, Ioannis Savidis:
Run-time voltage detection circuit for 3-D IC power delivery. SoCC 2014: 183-187 - 2013
- [j4]Ioannis Savidis, Selçuk Köse
Power Noise in TSV-Based 3-D Integrated Circuits. IEEE J. Solid State Circuits 48(2): 587-597 (2013) - 2011
- [j3]Jinhui Wang, Ioannis Savidis, Eby G. Friedman:
Thermal analysis of oxide-confined VCSEL arrays. Microelectron. J. 42(5): 820-825 (2011) - [j2]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2256-2266 (2011) - [c4]Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman:
Clock distribution models of 3-D integrated systems. ISCAS 2011: 2225-2228 - 2010
- [j1]Ioannis Savidis, Syed M. Alam, Ankur Jain, Scott Pozder, Robert E. Jones, Ritwik Chatterjee:
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectron. J. 41(1): 9-16 (2010) - [c3]Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang
An intra-chip free-space optical interconnect. ISCA 2010: 94-105
2000 – 2009
- 2008
- [c2]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock distribution networks for 3-D ictegrated Circuits. CICC 2008: 651-654 - [c1]Ioannis Savidis, Eby G. Friedman:
Electrical modeling and characterization of 3-D vias. ISCAS 2008: 784-787
Coauthor Index
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last updated on 2024-08-10 01:26 CEST by the dblp team
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