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Unai Bidarte
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2020 – today
- 2023
- [c23]Sara Alonso
, Jesús Lázaro, Jaime Jiménez, Leire Muguira
Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. DCIS 2023: 1-6 - 2022
- [j17]Jesús Lázaro
Embedded firewall for on-chip bus transactions. Comput. Electr. Eng. 98: 107707 (2022) - [c22]Sara Alonso
The influence of virtualization on real-time systems' interrupts in embedded SoC platforms. DCIS 2022: 1-6 - 2021
- [j16]Mikel Rodriguez
A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. IEEE Access 9: 51646-51658 (2021) - [j15]Jesús Lázaro
Fast and efficient address search in System-on-a-Programmable-Chip using binary trees. Comput. Electr. Eng. 96(Part): 107403 (2021) - [c21]Sara Alonso
Evaluating the OpenAMP framework in real-time embedded SoC platforms. DCIS 2021: 1-6
2010 – 2019
- 2019
- [j14]Marcelo Urbina
Smart Sensor: SoC Architecture for the Industrial Internet of Things. IEEE Internet Things J. 6(4): 6567-6577 (2019) - [c20]Carlos Cuadrado
Fast and efficient FPGA prototype system for embedded control algorithms in electric traction. DCIS 2019: 1-7 - 2018
- [j13]Igor Villalta, Unai Bidarte
SEU emulation in industrial SoCs combining microprocessor and FPGA. Reliab. Eng. Syst. Saf. 170: 53-63 (2018) - [c19]Mikel Rodriguez, Armando Astarloa
System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. DCIS 2018: 1-6 - 2017
- [j12]Marcelo Urbina
Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. IEEE Access 5: 20408-20417 (2017) - [j11]Igor Villalta, Unai Bidarte
Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. Microelectron. Reliab. 78: 85-92 (2017) - [j10]Naiara Moreira, Jesús Lázaro
On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. IEEE Trans. Smart Grid 8(4): 1932-1942 (2017) - 2016
- [j9]Uli Kretzschmar, Julen Gomez-Cornejo
Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. Reliab. Eng. Syst. Saf. 151: 1-9 (2016) - [c18]Armando Astarloa
Intelligent gateway for Industry 4.0-compliant production. IECON 2016: 4902-4907 - 2015
- [c17]Armando Astarloa
FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. ReConFig 2015: 1-6 - 2014
- [c16]Igor Villata, Unai Bidarte
Fast and accurate SEU-tolerance characterization method for Zynq SoCs. FPL 2014: 1-4 - 2013
- [c15]Julen Gomez-Cornejo
Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON 2013: 2261-2266 - [c14]Armando Astarloa
System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON 2013: 2329-2334 - 2011
- [j8]Jesús Lázaro
I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. 57(2): 206-213 (2011) - [c13]Uli Kretzschmar, Armando Astarloa
Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. ReConFig 2011: 255-260 - 2010
- [j7]Taho Dorta
Reconfigurable Multiprocessor Systems: A Review. Int. J. Reconfigurable Comput. 2010: 570279:1-570279:10 (2010) - [c12]Armando Astarloa
An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) 2010: 281-290
2000 – 2009
- 2009
- [c11]Jesús Lázaro
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC 2009: 312-317 - [c10]Armando Astarloa, Jesús Lázaro
DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops 2009: 472-475 - [c9]Armando Astarloa
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig 2009: 54-58 - [c8]Taho Dorta, Jaime Jimenez, José Luis Martín
Overview of FPGA-Based Multiprocessor Systems. ReConFig 2009: 273-278 - 2008
- [c7]Armando Astarloa
Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ATC 2008: 603-614 - [c6]Armando Astarloa
Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. ReConFig 2008: 169-174 - 2007
- [j6]Jesús Lázaro
Hardware architecture for a general regression neural network coprocessor. Neurocomputing 71(1-3): 78-87 (2007) - [j5]Armando Astarloa
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. 53(9): 629-643 (2007) - [j4]Jaime Jimenez, José Luis Martín
Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. 56(6): 3695-3708 (2007) - 2006
- [j3]Jaime Jimenez, José Luis Martín
Comparison of two designs for the multifunction vehicle bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 797-805 (2006) - 2005
- [j2]José L. Martín-Sánchez, Aitzol Zuloaga
Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. 98(3): 462-490 (2005) - [j1]Armando Astarloa
Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems 29(10): 421-434 (2005) - 2004
- [c5]Unai Bidarte
Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. FPL 2004: 965-969 - [c4]Jesús Lázaro
High Throughput Serpent Encryption Implementation. FPL 2004: 996-1000 - [c3]Armando Astarloa
A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL 2004: 1124-1126 - [c2]Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga:
Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS 2004: 17-22 - 2003
- [c1]Unai Bidarte
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL 2003: 497-506
Coauthor Index
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