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Julius Edler
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2020 – today
- 2023
- [j1]Marcel Runge
, Julius Edler
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. IEEE J. Solid State Circuits 58(8): 2288-2299 (2023) - [c5]Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers:
A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. NEWCAS 2023: 1-5 - [c4]Julius Edler
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c3]Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers:
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. CICC 2022: 1-2 - 2021
- [c2]Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers:
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. CICC 2021: 1-2 - [c1]Julius Edler
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. MWSCAS 2021: 1090-1093
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