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C. Bernard Shung
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2000 – 2009
- 2008
- [j13]Jeffrey M. Gilbert, Chinh H. Doan, Sohrab Emami, C. Bernard Shung:
A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset. IEEE Micro 28(2): 56-64 (2008) - 2003
- [j12]Kuen-Rong Lo, Chung-Ju Chang, C. Bernard Shung:
A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services. IEEE Trans. Veh. Technol. 52(5): 1196-1206 (2003) - 2001
- [j11]Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee:
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. IEEE J. Solid State Circuits 36(2): 229-238 (2001) - 2000
- [j10]Wei-Chang Tsai, C. Bernard Shung, Sheng-Jyh Wang:
Two systolic architectures for modular multiplication. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 103-107 (2000) - [j9]Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung:
A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems. IEEE Trans. Veh. Technol. 49(5): 1588-1598 (2000)
1990 – 1999
- 1999
- [j8]Hsie-Chia Chang, C. Bernard Shung:
New serial architecture for the Berlekamp-Massey algorithm. IEEE Trans. Commun. 47(4): 481-483 (1999) - 1998
- [j7]Kuen-Rong Lo, Chung-Ju Chang, Cooper Chang, C. Bernard Shung:
A combined channel assignment mechanism for hierarchical cellular systems. Comput. Commun. 21(13): 1143-1152 (1998) - [c9]Hsie-Chia Chang, C. Bernard Shung:
A (208, 192;8) Reed-Solomon decoder for DVD application. ICC 1998: 957-960 - 1997
- [j6]Yu-Sheng Lin, C. Bernard Shung:
Quasi-pushout cell discarding. IEEE Commun. Lett. 1(5): 146-148 (1997) - [j5]Wei-Chang Tsai, C. Bernard Shung:
Event-Driven Power Estimation of CMOS Circuits. J. Circuits Syst. Comput. 7(5): 471-482 (1997) - [c8]Shu-Jen Fang, Yu-Sheng Lin, Shan-Chieh Yang, C. Bernard Shung:
Reactive Bandwidth Arbitration for Priority and Multicasting Control in ATM Switching. ICC (3) 1997: 1724-1728 - 1996
- [c7]Yu-Sheng Lin, C. Bernard Shung:
Queue Management for Shared Buffer and Shared Multi-Buffer ATM Switches. INFOCOM 1996: 688-695 - 1994
- [c6]Yeong-Fong Lin, C. Bernard Shung:
Fault-Tolerant Architectures for Shared Buffer Memory Switch. ISCAS 1994: 61-64 - 1993
- [j4]C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar:
Area-efficient architectures for the Viterbi algorithm. I. Theory. IEEE Trans. Commun. 41(4): 636-644 (1993) - [j3]C. Bernard Shung, Horng-Dar Lin, Robert Cypher, Paul H. Siegel, Hemant K. Thapar:
Area-efficient architectures for the Viterbi algorithm II. Applications. IEEE Trans. Commun. 41(5): 802-807 (1993) - [j2]Robert Cypher, C. Bernard Shung:
Generalized trace-back techniques for survivor memory management in the Viterbi algorithm. J. VLSI Signal Process. 5(1): 85-94 (1993) - [c5]Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform. ISCAS 1993: 1575-1578 - 1992
- [c4]Deborah C. Wang, C. Bernard Shung:
Crossing distribution. EURO-DAC 1992: 354-361 - 1991
- [j1]C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen:
An integrated CAD system for algorithm-specific IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 447-463 (1991) - [c3]Paul H. Siegel, C. Bernard Shung, Thomas D. Howell, Hemant K. Thapar:
Exact bounds for Viterbi detector path metric differences. ICASSP 1991: 1093-1096 - [c2]Horng-Dar Lin, C. Bernard Shung:
General in-place scheduling for the Viterbi algorithm. ICASSP 1991: 1577-1580 - 1990
- [c1]C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed:
Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels. ICCD 1990
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